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參數(shù)資料
| 型號： | AD7861APZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 11BIT 4CHAN 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 28.6k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 7 個單端，單極 |
AD7861
REV. B
–3–
Table I. AD7861 Timing Parameters (TA = –40 C to +85 C and VDD = +5 V unless otherwise noted)
Number
Symbol
AD7861 Timing Requirements
Min
Max
Units
1tsucsb_rdb
CS Low Before Falling Edge of RD
0–
ns
2tsuaddr_rdb
ADDR Valid Before Falling Edge of
RD
0–
ns
3tdlyrdb_data
DATA Valid After Falling Edge of
RD
–25
ns
4tpwlrdb
RD Pulsewidth, Low
25
–
ns
5tpwhrdb
RD Pulsewidth, High
25
–
ns
6thdrdb_data
DATA Hold After Rising Edge of
RD
10
–
ns
7thdrdb_addr
ADDR Hold After Rising Edge of
RD
0–
ns
8thdrdb_csb
CS Hold After Rising Edge of RD
0–
ns
9tperclk
CLK Period
80
160
ns
10
tpwhclk
CLK Pulsewidth, High
20
–
ns
11
tpwlclk
CLK Pulsewidth, Low
20
–
ns
12
tpwlresetb
RESET Pulsewidth, Low
2
× tperclk –
ns
7, 8
3
1, 2
CLK
CS
A0–A1
RD
DATA
BUS
6
4
5
Figure 1. Clock and Reset Timing
9
10
11
CLK
12
CLK
RESET
Figure 2. Write Cycle Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7861 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model
Temperature Range
Package Option
AD7861AP
–40
°C to +85°C
P-44A
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . –0.3 V to +7.0 V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Input Voltage . . . . . . . . . . .
–0.3 V to VDD
Digital Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD
Analog Reference Output Swing . . . . . . . . . . .
–0.3 V to VDD
Operating Temperature . . . . . . . . . . . . . . . . . –40
°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +280
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
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