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| 型號(hào)： | AD7859LASZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 18/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 8CH 200KSPS 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤(pán) |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 779 (CN2011-ZH PDF) |
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AD7859/AD7859L
REV. A
–25–
t11
t12
t11
t12
t13
t14
t15
t16
t17
LOW BYTE
HIGH BYTE
*W/B PIN LOGIC LOW
HBEN
CS
WR
DB0 – DB7
Figure 37. Write Cycle Timing for Byte Mode Operation
Writing
With W/B at a logic high, a single write operation transfers the
full data word to the AD7859. The DB8/HBEN pin assumes its
DB8 function. Data to be written to the AD7859 should be pro-
vided on the DB0–DB15 inputs with DB0 the LSB of the data
word. With W/B at a logic low, the AD7859 requires two write
operations to transfer a full 16-bit word. DB8/HBEN assumes
its HBEN function. Data to be written to the AD7859 should
be provided on the DB0–DB7 inputs. HBEN determines
whether the byte which is to be written is high byte or low byte
data. The low byte of the data word should be written first with
DB0 the LSB of the full data word. For the high byte write,
HBEN should be high and the data on the DB0 input should be
data bit 8 of the 16-bit word with the data on DB7 the MSB of
the 16-bit word.
Figure 35 shows the write cycle timing diagram for the AD7859.
When operated in word mode, the HBEN input does not exist
and only the first write operation is required to write data to the
AD7859. Data should be provided on DB0–DB15. When oper-
ated in byte mode, the two write cycles shown in Figure 37 are
required to write the full data word to the AD7859. In Figure 37,
the first write transfers the lower 8 bits of the full data from
DB0–DB7 and the second write transfers the upper 8 bits of the
data word from DB0-DB7.
The CS and WR signals are gated internally. CS and WR may
be tied together as the timing specification for t13 and t14 is 0 ns
min. The data is latched on the rising edge of WR. The data
needs to be set up a time t16 before the WR rising edge and held
for a time t17 after the WR rising edge.
Resetting the Parallel Interface
In the case where incorrect data is inadvertently written to the
AD7859, there is a possibility that the Test Register contents
may have been altered. If there is a suspicion that this may have
happened and the part is not operating as expected, a 16-bit
word 0000 0000 0000 0010 should be written to the AD7859 to
restore the Test Register contents to the default value.
MICROPROCESSOR INTERFACING
Interfacing the AD7859/AD7859L to a 16-Bit Data Bus
The parallel port on the AD7859 allows the device to be inter-
faced to microprocessors or DSP processors as a memory-
mapped or I/O-mapped device. The CS and RD inputs are
common to all memory peripheral interfacing. Typical inter-
faces to different processors are shown in Figures 38 to 42. In
all the interfaces shown, an external timer controls the CONVST
input of the AD7859/AD7859L, the BUSY output interrupts
the host DSP and the W/B input is logic high.
AD7859/AD7859L to ADSP-21xx
Figure 38 shows the AD7859/AD7859L interfaced to the
ADSP-21xx series of DSPs as a memory mapped device. A
single wait state may be necessary to interface the AD7859/
AD7859L to the ADSP-21xx depending on the clock speed of
the DSP. This wait state can be programmed via the Data
Memory Waitstate Control Register of the ADSP-21xx (please
see ADSP-2100 Family Users Manual for details). The following
instruction reads data from the AD7859/AD7859L:
MR = DM(ADC)
where ADC is the address of the AD7859/AD7859L.
ADSP-21xx*
CS
DB15–DB0
AD7859/
AD7859L*
*ADDITIONAL PINS OMITTED FOR CLARITY
D23–D8
ADDR
DECODE
DMS
DATA BUS
WR
RD
ADDRESS BUS
EN
WR
RD
IRQ2
A13–A0
BUSY
Figure 38. AD7859/AD7859L to ADSP-21xx Parallel
Interface
AD7859/AD7859L to TMS32020, TMS320C25 and TMS320C5x
Parallel interfaces between the AD7859/AD7859L and the
TMS32020, TMS320C25 and TMS320C5x family of DSPs are
shown in Figure 39. The memory mapped address chosen for
the AD7859/AD7859L should be chosen to fall in the I/O
memory space of the DSPs.
TMS32020/
TMS320C25/
TMS320C50*
CS
DB15–DB0
AD7859/
AD7859L*
*ADDITIONAL PINS OMITTED FOR CLARITY
D23–D0
ADDR
DECODE
DATA BUS
WR
RD
ADDRESS BUS
STRB
INTx
A15–A0
R/
W
EN
IS
MSC
READY
TMS320C25
ONLY
BUSY
Figure 39. AD7859/AD7859L to TMS32020/C25/C5x Parallel
Interface
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