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參數資料
| 型號： | AD7853LARS-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 34/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL 200KSPS 24-SSOP |
| 標準包裝： | 1,500 |
| 位數： | 12 |
| 采樣率（每秒）： | 100k |
| 數據接口： | 8051，QSPI?，串行，SPI? µP |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 33mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 24-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 1 個偽差分，單極；1 個偽差分，雙極 |
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REV. B
–9–
AD7853/AD7853L
ON-CHIP REGISTERS
The AD7853/AD7853L powers up with a set of default conditions, and the user need not ever write to the device. In this case the
AD7853/AD7853L will operate as a Read-Only ADC. The AD7853/AD7853L still retains the flexibility for performing a full power-
down, and a full self-calibration. Note that the DIN pin should be tied to DGND for operating the AD7853/AD7853L as a Read-
Only ADC.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7853/AD7853L contains a Control register, ADC output data register, Status register, Test register and 10 Calibra-
tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and
calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
A write operation to the AD7853/AD7853L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine
which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are writ-
ten that the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the over-
all write register hierarchy.
Table I. Write Register Addressing
ADDR1
ADDR0
Comment
0
This combination does not address any register so the subsequent 14 data bits are ignored.
0
1
This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register.
1
0
This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written
to the selected calibration register.
1
This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the
control register.
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register
until the read selection bits are changed in the control register.
Table II. Read Register Addressing
RDSLT1
RDSLT0
Comment
0
All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up
default setting. There will always be four leading zeros when reading from the ADC output data register.
0
1
All successive read operations will be from TEST REGISTER.
1
0
All successive read operations will be from CALIBRATION REGISTERS.
1
All successive read operations will be from STATUS REGISTER.
ADDR1, ADDR0
DECODE
CALIBRATION
REGISTERS
GAIN(1)
OFFSET(1)
01
10
11
CALSLT1, CALSLT0
DECODE
00
01
10
11
TEST
REGISTER
CONTROL
REGISTER
OFFSET(1)
GAIN(1)
OFFSET(1)
DAC(8)
Figure 4. Write Register Hierarchy/Address Decoding
RDSLT1, RDSLT0
DECODE
CALIBRATION
REGISTERS
GAIN(1)
OFFSET(1)
01
10
11
CALSLT1, CALSLT0
DECODE
00
01
10
11
TEST
REGISTER
STATUS
REGISTER
OFFSET(1)
GAIN(1)
OFFSET(1)
DAC(8)
ADC OUTPUT
DATA REGISTER
00
Figure 5. Read Register Hierarchy/Address Decoding
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