- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1984 > AD7853BNZ (Analog Devices Inc)IC ADC 12BIT SRL 200KSPS 24-DIP PDF資料下載
參數(shù)資料
| 型號： | AD7853BNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 34/34頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL 200KSPS 24-DIP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 15 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 8051，QSPI?，串行，SPI? µP |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 33mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極；1 個偽差分，雙極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁
REV. B
–9–
AD7853/AD7853L
ON-CHIP REGISTERS
The AD7853/AD7853L powers up with a set of default conditions, and the user need not ever write to the device. In this case the
AD7853/AD7853L will operate as a Read-Only ADC. The AD7853/AD7853L still retains the flexibility for performing a full power-
down, and a full self-calibration. Note that the DIN pin should be tied to DGND for operating the AD7853/AD7853L as a Read-
Only ADC.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7853/AD7853L contains a Control register, ADC output data register, Status register, Test register and 10 Calibra-
tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and
calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
A write operation to the AD7853/AD7853L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine
which register is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are writ-
ten that the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the over-
all write register hierarchy.
Table I. Write Register Addressing
ADDR1
ADDR0
Comment
0
This combination does not address any register so the subsequent 14 data bits are ignored.
0
1
This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register.
1
0
This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written
to the selected calibration register.
1
This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the
control register.
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register.
Once the read selection bits are set in the control register all subsequent read operations that follow will be from the selected register
until the read selection bits are changed in the control register.
Table II. Read Register Addressing
RDSLT1
RDSLT0
Comment
0
All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up
default setting. There will always be four leading zeros when reading from the ADC output data register.
0
1
All successive read operations will be from TEST REGISTER.
1
0
All successive read operations will be from CALIBRATION REGISTERS.
1
All successive read operations will be from STATUS REGISTER.
ADDR1, ADDR0
DECODE
CALIBRATION
REGISTERS
GAIN(1)
OFFSET(1)
01
10
11
CALSLT1, CALSLT0
DECODE
00
01
10
11
TEST
REGISTER
CONTROL
REGISTER
OFFSET(1)
GAIN(1)
OFFSET(1)
DAC(8)
Figure 4. Write Register Hierarchy/Address Decoding
RDSLT1, RDSLT0
DECODE
CALIBRATION
REGISTERS
GAIN(1)
OFFSET(1)
01
10
11
CALSLT1, CALSLT0
DECODE
00
01
10
11
TEST
REGISTER
STATUS
REGISTER
OFFSET(1)
GAIN(1)
OFFSET(1)
DAC(8)
ADC OUTPUT
DATA REGISTER
00
Figure 5. Read Register Hierarchy/Address Decoding
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7854BRZ | IC ADC 12BIT PARALLEL LP 28-SOIC |
| AD7856ARZ-REEL7 | IC ADC 14BIT 8CHAN 5V 24SOIC |
| AD7858LBNZ | IC ADC 12BIT 8CHAN SRL 24DIP |
| AD7859BSZ | IC ADC 12BIT 8CHAN LP 44-MQFP |
| AD7861AP | IC ADC 11BIT 4CH 44-PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7853BR | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SOIC W 制造商:Analog Devices 功能描述:Analog Devices AD7853BR Analog to Digital Converters (ADC) |
| AD7853BR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SOIC W T/R |
| AD7853BRZ | 功能描述:IC ADC 12BIT SRL 200KSPS 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7853BRZ-REEL | 功能描述:IC ADC 12BIT SRL 200KSPS 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7853L | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
發(fā)布緊急采購，3分鐘左右您將得到回復。