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參數(shù)資料
| 型號(hào)： | AD7851KRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 11/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SRL 333KSPS 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 333k |
| 數(shù)據(jù)接口： | 8051，QSPI?，串行，SPI? µP |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 89.25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)偽差分，單極；1 個(gè)偽差分，雙極 |
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–19–
REV. B
AD7851
INPUT FREQUENCY (kHz)
–72
–74
–90
0.91
100
13.4
25.7
38.3
50.3
–76
–78
–80
–88
PSRR
(dB)
–82
–84
–86
63.5
74.8
87.4
AVDD = DVDD = 5.0V
100mV pk-pk SINEWAVE ON AVDD
REFIN = 4.098 EXT REFERENCE
Figure 22. PSRR vs. Frequency
POWER-DOWN OPTIONS
The AD7851 provides flexible power management to allow the
user to achieve the best power performance for a given throughput
rate. The power management options are selected by programming
the power management bits, PMGT1 and PMGT0, in the con-
trol register and by use of the
SLEEP pin. Table VI summarizes
the power-down options that are available and how they can be
selected by using either software, hardware, or a combination of
both. The AD7851 can be fully or partially powered down. When
fully powered down, all the on-chip circuitry is powered down
and IDD is 1
A typ. If a partial power-down is selected, then all
the on-chip circuitry except the reference is powered down and IDD
is 400
A typ. The choice of full or partial power-down does not
give any significant improvement in throughput with a power-down
between conversions. (This is discussed in the Power-Up Times
section which follows.) But a partial power-down does allow the
on-chip reference to be used externally even though the rest of the
AD7851 circuitry is powered down. It also allows the AD7851 to
be powered up faster after a long power-down period when using
the on-chip reference. (See the Using the Internal (On-Chip) Ref-
erence section which follows.)
When using the
SLEEP pin, the power management bits
PMGT1 and PMGT0 should be set to 0 (default status on
power-up). Bringing the
SLEEP pin logic high ensures normal
operation, and the part does not power down at any stage. This
may be necessary if the part is being used at high throughput
rates when it is not possible to power down between conver-
sions. If the user wishes to power down between conversions at
lower throughput rates (that is, <100 kSPS for the AD7851) to
achieve better power performances, then the
SLEEP pin should
be tied logic low.
If the power-down options are to be selected in software only,
then the
SLEEP pin should be tied logic high. By setting the
power management bits PMGT1 and PMGT0 as shown in
Table VI, a full power-down, full power-up, full power-down
between conversions, and a partial power-down between con-
versions can be selected.
A combination of hardware and software selection can also be
used to achieve the desired effect.
Table VI. Power Management Options
PMGT1
PMGT0
SLEEP
Bit
Pin
Comment
00
0
Full power-down between
conversions (HW/SW)
00
1
Full power-up (HW/SW)
01
X
Full power-down between
conversions (SW)
10
X
Full power-down (SW)
11
X
Partial power-down between
conversions (SW)
SW = Software selection, HW = Hardware selection.
0V TO VREF
INPUT
DIN AT DGND
=> NO WRITING
TO DEVICE
3-WIRE MODE
SELECTED
CURRENT, I = 12mA TYP
AVDD
DVDD
AIN(+)
AIN(–)
AMODE
CREF1
CREF2
SLEEP
DIN
DOUT
SYNC
SM1
SM2
CONVST
AGND
DGND
CLKIN
SCLK
REFIN/REFOUT
POLARITY
AD7851
ANALOG
(5V)
0.01 F
0.1 F
10 F
DVDD
UNIPOLAR RANGE
0.01 F
SERIAL MODE
SELECTION BITS
MASTER
CLOCK
INPUT
CONVERSION
START INPUT
SERIAL DATA OUTPUT
0.1 F
CAL
INTERNAL
REFERENCE
6MHz/7MHz
OSCILLATOR
SERIAL CLOCK OUTPUT
285kHz/ 333kHz PULSE
GENERATOR
OPTIONAL
EXTERNAL
REFERENCE
0.01 F
0.1 F
470nF
AUTO CAL ON
POWER-UP
REF198
AUTO POWER-
DOWN AFTER
CONVERSION
LOW POWER
C/ P
Figure 23. Typical Low Power Circuit
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