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參數(shù)資料
| 型號： | AD7849CRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14/16BIT SRL-IN 20-SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 設(shè)置時間： | 7µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 143k |
AD7849
Rev. C | Page 15 of 20
Other Output Voltage Ranges
In some cases, users may require output voltage ranges other than
those already mentioned. One example is systems that need the
output voltage to be a whole number of millivolts (that is,1 mV or
2 mV). If the circuit shown in Figure 22 is used, then the LSB size is
125 μV. This makes it possible to program whole millivolt values at
the output. Table 9 shows the code table for the circuit shown in
VDD
VCC
VREF+
VOUT
(0V TO 8.192V)
DGND
VREF–
AD7849*
AD584
SIGNAL
GND
1
*ADDITIONAL PINS OMITTED FOR CLARITY.
8
4
ROFS
AGND
R2
R1 8.192V
+15V
+5V
010
08-
023
Figure 22. 0 V to 8.192 V Output Range
Table 9. Code Table for Figure 22
Binary Number in DAC Latch
MSB
LSB
Analog Output (VOUT)
1111 1111 1111 1111
8.192 V (65,535/65,536) = 8.1919 V
1000 0000 0000 0000
8.192 V (32,768/65,536) = 4.096 V
0000 0000 0000 1000
8.192 V (8/65,536) = 0.001 V
0000 0000 0000 0100
8.192 V (4/65,536) = 0.0005 V
0000 0000 0000 0010
8.192 V (2/65,536) = 0.00025 V
0000 0000 0000 0001
8.192 V (1/65,536) = 0.000125 V
Generating a ±5 V Output Range from a Single +5 V
Reference
Figure 23 shows how to generate a ±5 V output range when
using a single +5 V reference. VREF is connected to 0 V, and ROFS
is connected to VREF+. The 5 V reference input is applied to these
pins. With all 0s loaded to the DAC, the noninverting terminal
of the output stage amplifier is at 0 V, and VOUT is the inverse of
VREF+. With all 1s loaded to the DAC, the noninverting terminal of
the output stage amplifier is 5 V and, therefore, VOUT is also 5 V.
ROFS
VDD
VCC
VREF+
VOUT
(–5V TO +5V)
DGND
VREF–
VSS
–15V
AD7849*
R1
10k
AD586
C1
1nF
SIGNAL GND
6
8
4
5
*ADDITIONAL PINS OMITTED FOR CLARITY.
2
AGND
+15V
+5V
01
00
8-
02
4
Figure 23. Generating a ±5 V Output Range from a Single +5 V
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD7849 is via a serial bus
that uses standard protocol compatible with DSP processors
and microcontrollers. The communications channel requires a
3-wire interface consisting of a clock signal, a data signal, and a
synchronization signal. The AD7849 requires a 16-bit data-word
with data valid on the falling edge of SCLK. For all the interfaces,
the DAC update can be done automatically when all data is
clocked in, or it can be done under control of LDAC.
interfacing to a number of popular DSP processors and
microcontrollers.
AD7849-to-DSP56000 Interface
A serial interface between the AD7849 and the DSP56000 is
shown in Figure 24. The DSP56000 is configured for normal
mode asynchronous operation with a gated clock. It is also
setup for a 16-bit word with SCK and SC2 as outputs and the
FSL control bit set to 0. SCK is internally generated on the
DSP56000 and applied to the AD7849 SCLK input. Data from
the DSP56000 is valid on the falling edge of SCK. The SC2 output
provides the framing pulse for valid data. This line must be
inverted before being applied to the SYNC input of the
.
In this interface, an LDAC pulse generated from an external timer
is used to update the outputs of the DAC. This update can also
be produced using a bit programmable control line from the
DSP56000.
DSP56000
SCK
STD
SC2
AD7849*
LDAC
SCLK
SDIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
TIMER
01008-029
Figure 24. AD7849-to-DSP56000 Interface
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