VREF+ VREF– DAC1 SEGMEN" />
參數(shù)資料
型號(hào): AD7846JP-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 4/24頁(yè)
文件大小: 0K
描述: IC DAC 16BIT MONO V-OUT 28-PLCC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 750
設(shè)置時(shí)間: 7µs
位數(shù): 16
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 雙 ±
功率耗散(最大): 100mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 143k
AD7846
Rev. G | Page 12 of 24
S1
VREF+
VREF–
DAC1
SEGMENT 1
SEGMENT 16
S3
S15
S17
S16
S14
S4
S2
DAC2
DAC3
12-BIT DAC
DB11 TO DB0
DB15 TO DB12
R
VOUT
RIN
A3
A2
A1
08
49
0-
0
21
Figure 21. Digital-to-Analog Conversion
OUTPUT STAGE
The output stage of the AD7846 is shown in Figure 22. It is capable
of driving a 2 kΩ/1000 pF load. It also has a resistor feedback
network that allows the user to configure it for gains of 1 or 2.
Table 6 shows the different output ranges that are possible.
An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately 2.5 μs
after the leading edge of LDAC. This short state keeps the DAC
output at its previous voltage while the AD7846 is internally
changing to its new value. Thus, any glitches that occur in the
transition are not seen at the output. In systems where the
LDAC is tied permanently low, the deglitching is not in
operation.
and
show the outputs of the
AD7846 without and with the deglitcher.
C1
LDAC
VOUT
RIN
DAC3
ONE
SHOT
10k
0
849
0-
0
22
Figure 22. Output Stage
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