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參數(shù)資料
| 型號(hào)： | AD7841BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 13/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT OCTAL V-OUT 44-MQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 31µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 303mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤(pán) |
| 輸出數(shù)目和類型： | 8 電壓，單極；8 電壓，雙極 |
| 采樣率（每秒）： | 32k |
| 產(chǎn)品目錄頁(yè)面： | 785 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7841EBZ-ND - BOARD EVAL FOR AD7841 |
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AD7841
–9–
Power-On with
CLR Low
The output stage of the AD7841 has been designed to allow
output stability during power-on. If
CLR is kept low during
power-on, then just after power is applied to the AD7841, the
situation is as depicted in Figure 5. G1, G4 and G6 are open
while G2, G3 and G5 are closed.
G1
G2
G4
G3
G6
G5
DUTGND
VOUT
R
14k
DAC
Figure 5. Output Stage with VDD < 7 V or VSS > –3 V; CLR
Low
VOUT is kept within a few hundred millivolts of DUTGND via
G5 and a 14 k
resistor. This thin-film resistor is connected in
parallel with the gain resistors of the output amplifier. The
output amplifier is connected as a unity gain buffer via G3, and
the DUTGND voltage is applied to the buffer input via G2. The
amplifier’s output is thus at the same voltage as the DUTGND
pin. The output stage remains configured as in Figure 5 until
the voltage at VDD exceeds 7 V and VSS is more negative than
–3 V. By now the output amplifier has enough headroom to
handle signals at its input and has also had time to settle. The
internal power-on circuitry opens G3 and G5 and closes G4 and
G6. This situation is shown in Figure 6. Now the output ampli-
fier is configured in its noise gain configuration via G4 and G6.
The DUTGND voltage is still connected to the noninverting
input via G2 and this voltage appears at VOUT.
G1
G2
G4
G3
G6
G5
DUTGND
VOUT
R
14k
DAC
Figure 6. Output Stage with VDD > 7 V and VSS < –3 V; CLR
Low
VOUT has been disconnected from the DUTGND pin by the
opening of G5, but will track the voltage present at DUTGND
via the configuration shown in Figure 6.
When
CLR is taken back high, the output stage is configured as
shown in Figure 7. The internal control logic closes G1 and
opens G2. The output amr})fier is connected in a noninverting
gain-of-two configuration. The voltage that appears on the VOUT
pins is determined by the data present in the DAC registers.
G1
G2
G4
G3
G6
G5
DUTGND
VOUT
R
14k
DAC
Figure 7. Output Stage After
CLR Is Taken High
Power-On with
CLR High
If
CLR is high on the application of power to the device, the
output stages of the AD7841 are configured as in Figure 8 while
VDD is less than 7 V and VSS is more positive than –3 V. G1 is
closed and G2 is open, thereby connecting the output of the
DAC to the input of its output amplifier. G3 and G5 are closed
while G4 and G6 are open, thus connecting the output amplifier as
a unity gain buffer. VOUT is connected to DUTGND via G5
through a 14 k
resistor until V
DD exceeds 7 V and VSS is more
negative than –3 V.
G1
G2
G4
G3
G6
G5
DUTGND
VOUT
R
14k
DAC
Figure 8. Output Stage Powering Up with
CLR High
While VDD < 7 V or VSS > –3 V
When the difference between the supply voltages reaches 10 V,
the internal power-on circuitry opens G3 and G5 and closes G4
and G6 configuring the output stage as shown in Figure 9.
G1
G2
G4
G3
G6
G5
DUTGND
VOUT
R
14k
DAC
Figure 9. Output Stage Powering Up with
CLR High
When VDD > 7 V and VSS < –3 V
REV. B
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