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參數(shù)資料
| 型號： | AD7837BNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL MULT 24DIP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 15 |
| 設置時間： | 4µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 210mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 250k |
AD7837/AD7847
REV. C
–7–
CIRCUIT INFORMATION
D/A SECTION
A simplified circuit diagram for one of the D/A converters and
output amplifier is shown in Figure 10.
A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A-C. The
remaining 10 bits drive the switches (S0–S9) in a standard R-2R
ladder configuration.
Each of the switches A–C steers 1/4 of the total reference cur-
rent with the remaining 1/4 passing through the R-2R section.
The output amplifier and feedback resistor perform the current
to voltage conversion giving
VOUT = – D
× VREF
where D is the fractional representation of the digital word. (D
can be set from 0 to 4095/4096.)
The output amplifier can maintain
±10 V across a 2 k load. It
is internally compensated and settles to 0.01% FSR (1/2 LSB)
in less than 5
s. Note that on the AD7837, VOUT must be con-
nected externally to RFB.
VOUT
R/2
R
VREF
2R
S0
AGND
R
2R
R
2R
S8
S9
A
B
C
SHOWN FOR ALL 1s ON DAC
Figure 10. D/A Simplified Circuit Diagram
INTERFACE LOGIC INFORMATION—AD7847
The input control logic for the AD7847 is shown in Figure 11.
The part contains a 12-bit latch for each DAC. It can be treated
as two independent DACs, each with its own
CS input and a com-
mon
WR input. CSA and WR control the loading of data to the
DAC A latch, while
CSB and WR control the loading of the
DAC B latch. The latches are edge triggered so that input data
is latched to the respective latch on the rising edge of
WR. If CSA
and
CSB are both low and WR is taken high, the same data will
be latched to both DAC latches. The control logic truth table is
shown in Table I, while the write cycle timing diagram for the
part is shown in Figure 12.
CSA
WR
CSB
DAC A LATCH
DAC B LATCH
Figure 11. AD7847 Input Control Logic
Table I. AD7847 Truth Table
C
CSA
CSB
WR
Function
X
1
No Data Transfer
1
X
No Data Transfer
01
g
Data Latched to DAC A
10
g
Data Latched to DAC B
00
g
Data Latched to Both DACs
g
1
0
Data Latched to DAC A
1
g
0
Data Latched to DAC B
gg
0
Data Latched to Both DACs
X = Don’t Care.
g = Rising Edge Triggered.
VALID
DATA
t1
t2
t3
t5
t4
CSA, CSB
WR
DATA
Figure 12. AD7847 Write Cycle Timing Diagram
INTERFACE LOGIC INFORMATION—AD7837
The input loading structure on the AD7837 is configured for
interfacing to microprocessors with an 8-bit-wide data bus. The
part contains two 12-bit latches per DAC—an input latch and
a DAC latch. Each input latch is further subdivided into a least-
significant 8-bit latch and a most-significant 4-bit latch. Only the
data held in the DAC latches determines the outputs from the part.
The input control logic for the AD7837 is shown in Figure 13,
while the write cycle timing diagram is shown in Figure 14.
DAC A MS
INPUT
LATCH
12
DAC A LS
INPUT
LATCH
4
8
DAC B LS
INPUT
LATCH
DAC B LS
INPUT
LATCH
12
4
8
CS
WR
DAC A
LATCH
LDAC
A0
A1
DB7 DB0
DAC B
LATCH
Figure 13. AD7837 Input Control Logic
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