參數(shù)資料
型號(hào): AD7829BRWZ-1RL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 2/20頁(yè)
文件大?。?/td> 0K
描述: IC ADC 8BIT 8CH 2MSPS 28-SOIC
標(biāo)準(zhǔn)包裝: 400
位數(shù): 8
采樣率(每秒): 2M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 36mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個(gè)單端,單極
AD7829-1
Rev. 0 | Page 10 of 20
CIRCUIT INFORMATION
TIMING AND
CONTROL
LOGIC
R1
HOLD
SAMPLING
CAPACITOR
A
B
SW2
R16
R15
R14
R13
T/H 1
VIN
D7
D6
D5
D4
D3
D2
D1
D0
DE
CO
DE
LOGIC
14
15
13
1
OU
TP
U
T
RE
G
IS
T
E
R
OU
TP
U
T
DRI
V
E
RS
REFERENCE
061
79-
006
CIRCUIT DESCRIPTION
The AD7829-1 consists of a track-and-hold amplifier followed
by a half-flash analog-to-digital converter. These devices use a
half-flash conversion technique where one 4-bit flash ADC is
used to achieve an 8-bit result. The 4-bit flash ADC contains a
sampling capacitor followed by 15 comparators that compare
the unknown input to a reference ladder to achieve a 4-bit result.
This first flash, that is, coarse conversion, provides the four
MSBs. For a full 8-bit reading to be realized, a second flash,
that is, a fine conversion, must be performed to provide the four
LSBs. The 8-bit word is then placed on the data output bus.
Figure 4 and Figure 5 show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes
into hold mode and holds the analog input for 120 ns. This is
the acquisition phase as shown in Figure 4, when Switch 2 is in
Position A. At the point when the track-and-hold returns to its
track mode, this signal is sampled by the sampling capacitor as
Switch 2 moves into Position B. The first flash occurs at this
instant and is then followed by the second flash. Typically, the
first flash is complete after 100 ns, that is, at 220 ns, while the
end of the second flash and, hence, the 8-bit conversion result,
is available at 330 ns (minimum). The maximum conversion
time is 420 ns. As shown in
Figure 5. ADC Conversion Phase
HOLD
120ns
CONVST
EOC
CS
RD
DB0 TO DB7
t2
TRACK
VALID
DATA
t1
t3
0
6179-
007
Figure 6, the track-and-hold returns
to track mode after 120 ns and starts the next acquisition before
the end of the current conversion. Figure 8 shows the ADC
transfer function.
TIMING AND
CONTROL
LOGIC
R1
HOLD
SAMPLING
CAPACITOR
A
B
SW2
R16
R15
R14
R13
T/H 1
VIN
D7
D6
D5
D4
D3
D2
D1
D0
DE
CO
DE
LOGIC
14
15
13
1
OU
TP
U
T
R
E
G
IST
ER
OU
TP
U
T
DRI
V
E
RS
REFERENCE
06179-
005
Figure 6. Track-and-Hold Timing
TYPICAL CONNECTION DIAGRAM
Figure 7 shows a typical connection diagram for the AD7829-1.
The AGND and DGND are connected together at the device for
good noise suppression. The parallel interface is implemented
using an 8-bit data bus. The end of conversion signal (EOC) idles
high, the falling edge of CONVST initiates a conversion, and at
the end of conversion the falling edge of EOC is used to initiate
an interrupt service routine (ISR) on a microprocessor (see the
Parallel Interface section). VREF IN/OUT and VMID are connected to a
voltage source, such as the AD780, while VDD is connected to a
voltage source that can vary from 4.5 V to 5.5 V (see Table 5 in
the Analog Input section). When VDD is first connected, the
AD7829-1 powers up in a low current mode, that is, power-down.
Ensure that the CONVST line is not floating when VDD is applied,
because this can put the AD7829-1 into an unknown state.
Figure 4. ADC Acquisition Phase
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