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參數(shù)資料
| 型號： | AD7829BRW-1RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 8CH 2MSPS 28-SOIC |
| 標準包裝： | 400 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 36mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
AD7829-1
Rev. 0 | Page 14 of 20
INPUT FREQUENCY (MHz)
50
38
0
1
0.2
1
S
NR
(
d
B)
3
4568
48
46
44
42
40
fSAMPLE = 2MHz
06
17
9-
0
17
CONVST
If the falling edge of
occurs after the required power-
up time has elapsed, then it is upon this falling edge that a
conversion is initiated. When using the on-chip reference, it is
necessary to wait the required power-up time of approximately
25 μs before initiating a conversion. That is, a falling edge on
CONVST must not occur before the required power-up time
has elapsed, when VDD is first connected or after the AD7829-1
has been powered down using the CONVST pin, as shown in
POWER VS. THROUGHPUT
Superior power performance can be achieved by using the
automatic power-down (Mode 2) at the end of a conversion
(see the
Figure 16. SNR vs. Input Frequency on the AD7829-1
Operating Modes section).
POWER-UP TIMES
Figure 18 shows how the automatic power-down is implemented
using the CONVST signal to achieve the optimum power perform-
ance for the AD7829-1. The duration of the
The AD7829-1 has a 1 μs power-up time when using an
external reference and a 25 μs power-up time when using the
on-chip reference. When VDD is first connected, the AD7829-1
is in a low current mode of operation. Ensure that the
CONVST pulse is
set to be equal to or less than the power-up time of the devices
(see the
CONVST
Operating Modes section). As the throughput rate is
reduced, the device remains in its power-down state longer, and the
average power consumption over time drops accordingly.
line is not floating when VDD is applied. If there is a glitch on
CONVST while VDD is rising, the part attempts to power up
before VDD has fully settled and may enter an unknown state.
In order to carry out a conversion, the AD7829-1 must first be
powered up.
tPOWER-UP
1s
330ns
tCONVERT
POWER-DOWN
tCYCLE
10s @ 100kSPS
CONVST
0
61
79-
019
VDD
tPOWER-UP
1s
CONVST
VDD
CONVST
tPOWER-UP
25s
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
EXTERNAL REFERENCE
ON-CHIP REFERENCE
0617
9-
018
Figure 18. Automatic Power-Down
For example, if the AD7829-1 is operated in a continuous
sampling mode, with a throughput rate of 100 kSPS and using
an external reference, the power consumption is calculated as
follows. The power dissipation during normal operation is
36 mW, VDD = 3 V. If the power-up time is 1 μs and the conversion
time is 330 ns (@ +25°C), the AD7829-1 can be said to dissipate
36 mW (maximum) for 1.33 μs during each conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 μs and
the average power dissipated during each cycle is (1.33/10) ×
(36 mW) = 4.79 mW. This calculation uses the minimum
conversion time, thus giving the best-case power dissipation at
this throughput rate. However, the actual power dissipated
during each conversion cycle may increase, depending on the
actual conversion time (up to a maximum of 420 ns).
Figure 17. AD7829-1 Power-Up Time
CONVST
The AD7829-1 is powered up by a rising edge on the
pin. A conversion is initiated on the falling edge of CONVST.
first connected or after the AD7829-1 has been powered down
using the CONVST pin when using either the on-chip reference
or an external reference. When using an external reference, the
falling edge of CONVST may occur before the required power-
up time has elapsed. However, the conversion is not initiated on
the falling edge of CONVST but rather at the moment when the
part has completely powered up, that is, after 1 μs.
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