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參數(shù)資料
| 型號： | AD7823YRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2.7 V to 5.5 V, 4.5 us, 8-Bit ADC in 8-Lead microSOIC/DIP |
| 中文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MICRO, SOIC-8 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 155K |
| 代理商： | AD7823YRM |
AD7823
–6–
REV. B
CIRCUIT DESCRIPTION
Converter Operation
The AD7823 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to V
DD
. Figures
4 and 5 below show simplified schematics of the ADC. Figure 4
shows the ADC during its acquisition phase. SW2 is closed and
SW1 is in Position A; the comparator is held in a balanced
condition; and the sampling capacitor acquires the signal on
V
IN+
.
V
DD
/3
V
IN+
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
CONTROL
LOGIC
OSC
SAMPLING
CAPACITOR
ACQUISITION
PHASE
SW2
A
SW1
B
V
IN
–
Figure 4. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 5) SW2 will
open, and SW1 will move to Position B causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor in order to bring the com-
parator back into a balanced condition. When the comparator
is rebalanced, the conversion is complete. The control logic
generates the ADC output code. Figure 11 shows the ADC
transfer function.
V
DD
/3
V
IN+
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
SAMPLING
CAPACITOR
CONVERSION
PHASE
SW2
A
SW1
B
V
IN
–
Figure 5. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7823.
The serial interface is implemented using two wires; the rising
edge of
CONVST
enables the serial interface—see Serial
Interface section for more details. V
REF
is connected to a well
decoupled V
DD
pin to provide an analog input range of 0 V to
V
DD
. When V
DD
is first connected, the AD7823 powers up in
a low current mode, i.e., power-down. A rising edge on the
CONVST
input will cause the part to power up—see Operating
Modes. If power consumption is of concern, the automatic
power-down at the end of a conversion should be used to im-
prove power performance. See Power vs. Throughput Rate
section of the data sheet.
D
OUT
SCLK
V
REF
AGND
V
DD
V
IN+
V
IN
–
CONVST
SUPPLY
+2.7V TO +5.5V
0V TO V
INPUT
AD7823
0.1 F
TWO-WIRE
SERIAL
INTERFACE
C/ P
10 F
Figure 6. Typical Connection Diagram
Analog Input
Figure 7 shows an equivalent circuit of the analog input struc-
ture of the AD7823. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
The maximum current these diodes can conduct without caus-
ing irreversible damage to the part is 20 mA. The capacitor C2
is typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is a lumped component made up of
the on resistance of a multiplexer and a switch. This resistor is
typically about 125
. The capacitor C1 is the ADC sampling
capacitor and has a capacitance of 3.5 pF.
V
DD
V
IN+
C1
3.5pF
R1
125
V
DD
/3
D2
D1
C2
4pF
CONVERT PHASE
–
SWITCH OPEN
ACQUISITION PHASE
–
SWITCH CLOSED
Figure 7. Equivalent Analog Input Circuit
The analog input of the AD7823 is made up of a pseudo
differential pair, V
IN+
pseudo differential with respect to V
IN–
.
The signal is applied to V
IN+
but in the pseudo differential
scheme the sampling capacitor is connected to V
IN–
during
conversion—see Figure 8. This input scheme can be used to
remove offsets that exist in a system. For example, if a system
had an offset of 0.5 V, the offset could be applied to V
IN–
and
the signal applied to V
IN+
. This has the effect of offsetting the
input span by 0.5 V. It is only possible to offset the input span
when the reference voltage (V
REF
) is less than V
DD
– V
OFFSET
.
V
DD
/3
V
IN+
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
SAMPLING
CAPACITOR
CONVERSION
PHASE
SW2
V
IN
–
CHARGE
REDISTRIBUTION
DAC
V
OFFSET
V
IN
(+)
V
OFFSET
Figure 8. Pseudo Differential Input Scheme
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