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參數(shù)資料
| 型號(hào)： | AD7821TE |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS High Speed, mP-Compatible 8-Bit ADC with Track/Hold Function |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 249K |
| 代理商： | AD7821TE |
AD7821
REV. A
–7–
Figure 4. Power Supply as Reference.
Unipolar Operation (0 to + 5 V)
Figure 5. External Reference.
Bipolar Operation (–2.5 V to +2.5 V)
INPUT CURRE NT
T he analog input of the AD7821 behaves somewhat differently
to conventional A/D converters. T his is due to the ADC’s
sampled data comparators, which take varying amounts of input
current depending on the cycle of the converter.
T he equivalent input circuit of the AD7821 is shown in Figure
6. When a conversion ends (e.g., falling edge of
INT
, WR-RD
mode, t
RD
> t
INT L
) all the input switches are closed and V
IN
is
connected to the comparators of the internal LS and MS ADCs.
T herefore, V
IN
is connected to 31 one-pF input capacitors
simultaneously .
Figure 6. AD7821 Equivalent Input Circuit
T he input capacitors must charge to the input voltage through
the on resistance of the analog switches (about 2 k
to 5 k
).
In addition, about 12 pF of input stray capacitance must be
charged.
T he analog input can be modeled as an equivalent RC network
as shown in Figure 7. As R
S
(source impedance) increases, the
input capacitance takes longer to charge.
T he comparators track the analog input between conversions. A
minimum delay time (t
P
) of 350 ns is required between conver-
sions to allow for voltage source settling and comparator track-
ing time. T his allows input time constants of 50 ns without
settling time problems. T ypical total input capacitance values of
55 pF allow R
S
to be 0.9 k
without lengthening t
P
to give V
IN
more time to settle.
Figure 7. RC Network Model
INPUT T RANSIE NT S
T ransients on the analog input signal caused by charging
current flowing into V
IN
will not normally degrade the ADC’s
performance. In effect, the AD7821 does not “l(fā)ook” at the in-
put when these transients occur. T he comparators’ inputs track
V
IN
and are not sampled until the falling edge of
WR
(WR-RD
Mode) or
RD
(RD Mode), so at least 350 ns (t
P
) is provided to
charge the ADC’s input capacitance. It is, therefore, not neces-
sary to filter out these transients with an external capacitor at
the V
IN
terminal.
INHE RE NT T RACK -AND-HOLD
A major benefit of the AD7821’s input structure is its ability to
measure a variety of high-speed signals without the help of an
external track-and-hold. Any ADC which does not have a built-
in track-and-hold, regardless of its speed, requires the analog in-
put to remain stable to at least 1/2 LSB for the duration of the
conversion to maintain full accuracy. T his requires the use of a
track-and-hold whenever the input is a high-speed signal. T he
AD7821’s sampled-data comparators, by nature of their input
switching, inherently accomplish this track-and-hold function.
Although the conversion time for the AD7821 is 660 ns
(WR-RD mode, t
WR
+ t
RD
+ t
ACC1
), the time for which V
IN
must
be stable to 1/2 LSB is much smaller. T he AD7821 tracks V
IN
between conversions only, and its value on the falling edge of
WR
or
RD
in the WR-RD or RD modes, respectively, is the
measured value.
SINUSOIDAL INPUT S
T he bandwidth of the built-in track-and-hold is 100 kHz max
(150 kHz typ, 5 V p-p). T his is limited by the analog bandwidth
of the comparators and timing skew between the comparator
switches. T his means that the analog input frequency can be up
to 100 kHz without the aid of an external track-and-hold. T he
Nyquist criterion requires that the sampling rate be at least
twice the input frequency (i.e.,
≥
2
3
100 kHz). T his requires an
ideal antialiasing filter with an infinite roll-off. T o ease the prob-
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