參數(shù)資料
型號(hào)： AD7821KR
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： LC2MOS High Speed, mP-Compatible 8-Bit ADC with Track/Hold Function
中文描述： 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20
封裝： MS-013AC, SOIC-20
文件頁(yè)數(shù)： 3/12頁(yè)
文件大小： 249K
代理商： AD7821KR
AD7821
REV. A
–3–
TIMNGCHARACTERISTICS
1
(V
DD
= +5 V
±
5%, V
SS
= 0 V or –5 V
±
5%; Unipolar or Bipolar Input Range)
Limit at
T
, T
(K, B Versions)
Limit at
T
, T
(T Version)
Limit at +25
8
C
(All Versions)
Parameter
Units
Conditions/Comments
t
CSS
t
t
CSH
0
0
70
0
0
85
0
0
100
ns min
ns min
ns max
CS
to
RD
/
WR
Setup T ime
CS
to
RD
/
WR
Hold T ime
CS
to RDY Delay. Pull-Up
Resistor 5 k1.
Conversion T ime (RD Mode)
Data Access T ime (RD Mode)
C
L
= 20 pF
C
L
= 100 pF
RD
to
INT
Delay (RD Mode)
t
t
CRD
700
875
975
ns max
t
CRD
+ 25
t
CRD
+ 50
50
80
15
60
350
250
10
250
160
t
CRD
+ 30
t
CRD
+ 65
–
85
15
70
425
325
10
350
205
t
CRD
+ 35
t
CRD
+ 75
–
90
15
80
500
400
10
450
240
ns max
ns max
ns typ
ns max
ns min
ns max
ns min
ns min
μ
s max
ns min
ns min
t
INT H2
t
DH4
Data Hold T ime
t
P
t
WR
Delay T ime Between Conversions
Write Pulse Width
t
RD
t
READ1
Delay T ime between
WR
and
RD
Pulses
RD
Pulse Width (WR-RD Mode, see Figure 12b)
Determined by t
Data Access T ime (WR-RD Mode, see Figure 12b)
C
L
= 20 pF
C
L
= 100 pF
RD
to
INT
Delay
WR
to
INT
Delay
t
ACC13
160
185
150
380
500
65
205
235
185
–
610
75
240
275
220
–
700
85
ns max
ns max
ns max
ns typ
ns max
ns min
t
t
RI
t
READ2
RD
Pulse Width (WR-RD Mode, see Figure 12a)
Determined by t
Data Access T ime (WR-RD Mode, see Figure 12a)
C
L
= 20 pF
C
L
= 100 pF
WR
to
INT
Delay (Stand-Alone Operation)
Data Access T ime after
INT
(Stand-Alone Operation)
C
L
= 20 pF
C
L
= 100 pF
t
ACC23
65
90
80
75
110
100
85
130
120
ns max
ns max
ns max
t
IHWR2
t
ID3
30
45
35
60
40
70
ns max
ns max
NOT ES
1
Sample tested at +25
°
C to ensure compliance. All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
C
= 50 pF.
3
Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
a. High Z to V
OH
Figure 1. Load Circuits for Data Access Time Test
b. High Z to V
OL
a. V
OH
to High Z
Figure 2. Load Circuits for Data Hold Time Test
b. V
OL
to High Z
ORDE RING GUIDE
T otal
Unadjusted
E rror (LSB) Option
2
T emperature
Range
Package
Model
1
AD7821K N
AD7821K P
AD7821K R
AD7821BQ
AD7821T Q
AD7821T E
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
±
1 max
±
1 max
±
1 max
±
1 max
±
1 max
±
1 max
N-20
P-20A
R-20
Q-20
Q-20
E-20A
NOT ES
1
T o order MIL-ST D-883, Class B processed parts, add /883B to part
number. Contact local sales office for military data sheet.
2
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded
Chip Carrier; Q = Cerdip; R = SOIC.
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