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| 型號： | AD7814ARTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 123K |
| 描述： | IC TEMP SNSR 10BIT DGTL SOT23-6 |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 10,000 |
| 功能： | 溫度監(jiān)控系統(tǒng)（傳感器） |
| 傳感器類型： | 內(nèi)部 |
| 感應(yīng)溫度： | -55°C ~ 125°C |
| 精確度： | ±2°C |
| 拓?fù)洌?/td> | ADC，寄存器庫 |
| 輸出類型： | MICROWIRE?，QSPI?，SPI? |
| 輸出警報： | 無 |
| 輸出風(fēng)扇： | 無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 帶卷 (TR) |
REV. E
2
AD7814SPECIFICATIONS
1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TEMPERATURE SENSOR AND ADC
Accuracy
?.0
癈
T
A
= 0癈 to 85癈. V
DD
= 3 V to 5.5 V
2
?.5
癈
T
A
= 40癈 to 0癈. V
DD
= 3 V to 5.5 V
2
?.0
?.5
癈
T
A
= 55癈 to +125癈. V
DD
= 3 V to 5.5 V
Resolution
10
Bits
Update Rate, t
R
400
祍
Temperature Conversion Time
25
祍
SUPPLIES
Supply Voltage
2.7
5.5
V
For Specified Performance
Supply Current
Normal Mode
250
400
礎(chǔ)
Shutdown Mode (V
DD
= 5 V)
1.23
3
礎(chǔ)
Shutdown Mode (V
DD
= 3 V)
0.43
1
礎(chǔ)
Power Dissipation
80
礧
V
DD
= 3 V. Using Normal Mode
Power Dissipation
V
DD
= 3 V. Using Shutdown Mode
1 sps
3.7
礧
10 sps
3.9
礧
100 sps
5.8
礧
DIGITAL INPUT
3
Input High Voltage, V
IH
2.4
V
Input Low Voltage, V
IL
0.8
V
Input Current, I
IN
?
礎(chǔ)
V
IN
= 0 V to V
DD
Input Capacitance, C
IN
10
pF
All Digital Inputs
DIGITAL OUTPUT
3
Output High Voltage, V
OH
V
DD
0.3 V
I
SOURCE
= I
SINK
= 200 礎(chǔ)
Output Low Voltage, V
OL
0.4
V
I
OL
= 200 礎(chǔ)
Output Capacitance, C
OUT
50
pF
NOTES
1
All specifications apply for 55癈 to +125癈 unless otherwise stated.
2
For V
DD
= 2.7 V to 3 V and T
A
= 40癈 to +85癈, the typical temperature error is ?癈.
3
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
Parameter
Limit
Unit
Comments
t
1
0
ns min
CS to SCLK Setup Time
t
2
50
ns min
SCLK High Pulse Width
t
3
50
ns min
SCLK Low Pulse Width
t
4
4
35
ns max
Data Access Time After SCLK Falling Edge
t
5
20
ns min
Data Setup Time Prior to SCLK Rising Edge
t
6
0
ns min
Data Hold Time After SCLK Rising Edge
t
7
0
ns min
CS to SCLK Hold Time
t
8
4
40
ns max
CS to DOUT High Impedance
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
3
See Figure 2.
4
Measured with the load circuit of Figure 1.
Specifications subject to change without notice.
(T
A
= T
MIN
to T
MAX
, V
DD
= 2.7 V to 5.5 V, unless otherwise noted.)
(T
A
= T
MIN
to T
MAX
, V
DD
= 2.7 V to 5.5 V, unless otherwise noted.)
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