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參數(shù)資料
| 型號： | AD7813YRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT PARALLEL 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 400k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產(chǎn)品目錄頁面： | 779 (CN2011-ZH PDF) |
AD7813
–10–
REV. C
MICROPROCESSOR INTERFACING
The parallel port on the AD7813 allows the device to be inter-
faced to a range of many different microcontrollers. This section
explains how to interface the AD7813 with some of the more
common microcontroller parallel interface protocols.
AD7813 to 8051
Figure 16 shows a parallel interface between the AD7813 and
the 8051 microcontroller. The BUSY signal on the AD7813 pro-
vides an interrupt request to the 8051 when a conversion begins.
Port 0 of the 8051 may serve as an input or output port, or as in
this case when used together, may be used as a bidirectional
low-order address and data bus. The address latch enable out-
put of the 8051 is used to latch the low byte of the address dur-
ing accesses to the device, while the high-order address byte is
supplied from Port 2. Port 2 latches remain stable when the
AD7813 is addressed, as they do not have to be turned around
(set to 1) for data input as is the case for Port 0.
AD7813*
8051*
AD0–AD7
ALE
A8–A15
RD
INT
LATCH
DECODER
DB0–DB7
CS
RD
BUSY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. Interfacing to the 8051
AD7813 to PIC16C6x/7x
Figure 17 shows a parallel interface between the AD7813 and the
PIC16C64/65/74. The BUSY signal on the AD7813 provides
an interrupt request to the microcontroller when a conversion
begins. Of the PIC16C6x/7x range of microcontrollers only the
PIC16C64/65/74 can provide the option of a parallel slave port.
Port D of the microcontroller will operate as an 8-bit wide
parallel slave port when control bit PSPMODE in the TRISE
register is set. Setting PSPMODE enables the port pin RE0
to be the RD output and RE2 to be the CS output. For this
functionality, the corresponding data direction bits of the
TRISE register must be configured as outputs (reset to 0).
See PIC16/17 Microcontroller User Manual.
PIC16C6x/7x*
PSP0–PSP7
RD
INT
*ADDITIONAL PINS OMITTED FOR CLARITY
CS
AD7813*
DB0–DB7
CS
RD
BUSY
Figure 17. Interfacing to the PIC16C6x/7x
AD7813 to ADSP-21xx
Figure 18 shows a parallel interface between the AD7813 and
the ADSP-21xx series of DSPs. As before, the BUSY signal on
the AD7813 provides an interrupt request to the DSP when a
conversion begins.
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS
DECODE
LOGIC
EN
AD7813*
DB0–DB7
CS
RD
BUSY
ADSP-21xx*
D7–D0
DMS
A13–A0
RD
IRQ
Figure 18. Interfacing to the ADSP-21xx
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