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| 型號(hào)： | AD7813YN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | +2.7 V to +5.5 V, 400 kSPS 8-/10-Bit Sampling ADC |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 185K |
| 代理商： | AD7813YN |
AD7813
–8–
REV. B
Typical Performance Characteristics
THROUGHPUT
–
kSPS
P
–
10
1
0.01
0
50
5
10
15
20
25
30
35
40
45
0.1
Figure 10. Power vs. Throughput
0
–
60
–
100
d
–
10
–
50
–
70
–
90
–
30
–
40
–
80
–
20
FREQUENCY
–
kHz
0
174
17
35
52
70
87
105
122
140
157
AD7813
2048 POINT FFT
SAMPLING 357.142kHz
FIN 30.168kHz
Figure 11. SNR
TIMING AND CONTROL
The AD7813 has only one input for timing and control, i.e.,
the
CONVST
(convert start signal). The rising edge of this
CONVST
signal initiates a 1
μ
s pulse on an internally generated
CONVST
signal. This pulse is present to ensure the part has
enough time to power up before a conversion is initiated. If the
external
CONVST
signal is low, the falling edge of the internal
CONVST
signal will cause the sampling circuit to go into
hold mode and initiate a conversion. If, however, the external
CONVST
signal is high when the internal
CONVST
goes low,
it is upon the falling edge of the external
CONVST
signal that
the sampling circuitry will go into hold mode and initiate a
conversion. The use of the internally generated 1
μ
s pulse, as
previously described, can be likened to the configuration
shown in Figure 12. The application of a
CONVST
signal at
the
CONVST
pin triggers the generation of a 1
μ
s pulse. Both
the external
CONVST
and this internal
CONVST
are input to
an OR gate. The resulting signal has the duration of the longer
of the two input signals. Once a conversion has been initiated
the BUSY signal goes high to indicate a conversion is in progress.
At the end of conversion the sampling circuit goes back into its
tracking mode again. The end of conversion is indicated by the
BUSY
signal going low. This signal may be used to initiate an
ISR on a microprocessor. At this point the conversion result is
latched into the output register where it may be read. The AD7813
has an 8-bit wide parallel interface. The 10-bit conversion result
is accessed by performing two successive read operations. The
first 8-bit read accesses the 8 MSBs of the conversion result and
the second read accesses the 2 LSBs, as illustrated in Figure 13,
where one performance of the two successive reads is highlighted
after the falling edge of BUSY. The state of the external
CONVST
signal at the end of conversion also establishes the mode of opera-
tion of the AD7813.
Mode 1 Operation (High Speed Sampling)
If the external
CONVST
is logic high when BUSY goes low, the
part is said to be in Mode 1 operation. While operating in Mode
1, the AD7813 will not power down between conversions. The
AD7813 should be operated in Mode 1 for high speed sampling
applications, i.e., throughputs greater than 100 kSPS. Figure 13
shows the timing for Mode 1 operation. From this diagram one
can see that a minimum delay of the sum of the conversion time
and read time must be left between two successive falling edges
of the external
CONVST
. This is to ensure that a conversion is
not initiated during a read.
Mode 2 Operation (Automatic Power-Down)
At slower throughput rates the AD7813 may be powered down
between conversions to give a superior power performance.
This is Mode 2 Operation and it is achieved by bringing the
CONVST
signal logic low before the falling edge of BUSY.
Figure 14, overleaf, shows the timing for Mode 2 Operation.
The falling edge of the external
CONVST
signal may occur
before or after the falling edge of the internal
CONVST
signal,
but it is the later occurring falling edge of both that controls
when the first conversion will take place. If the falling edge
of the external
CONVST
occurs after that of the internal
CONVST,
it means that the moment of the first conversion is
controlled exactly, regardless of any jitter associated with the
internal
CONVST
signal. The parallel interface is still fully
operational while the AD7813 is powered down. The AD7813
is powered up again on the rising edge of the
CONVST
signal.
The gated
CONVST
pulse will now remain high long enough
for the AD7813 to fully power up, which takes about 1
μ
s. This is
ensured by the internal
CONVST
signal, which will remain high
for 1
μ
s.
1 s
EXT
INT
CONVST
(PIN 4)
GATED
Figure 12.
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| AD7813YNZ | 功能描述:IC ADC 10BIT PARALLEL 16-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| AD7813YR | 制造商:Analog Devices 功能描述:ADC Single SAR 400ksps 10-bit Parallel 16-Pin SOIC N 制造商:Analog Devices 功能描述:IC 10-BIT ADC |
| AD7813YR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 400ksps 10-bit Parallel 16-Pin SOIC N T/R |
| AD7813YR-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 400ksps 10-bit Parallel 16-Pin SOIC N T/R |
| AD7813YRU | 功能描述:IC ADC 10BIT PARALLEL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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