參數(shù)資料
型號(hào): AD7805BN
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: %2B3.3V to %2B5V Quad/Octal 10-Bit DACs
中文描述: PARALLEL, WORD INPUT LOADING, 1.5 us SETTLING TIME, 10-BIT DAC, PDIP28
封裝: PLASTIC, DIP-28
文件頁(yè)數(shù): 5/28頁(yè)
文件大?。?/td> 300K
代理商: AD7805BN
AD7804/AD7805/AD7808/AD7809
–5–
REV. A
AD7805/AD7809 TIMING CHARACTERISTICS
1
= Internal Reference. All specifications T
MIN
to T
MAX
unless otherwise noted.)
(V
DD
= 3.3 V
6
10% to 5 V
6
10%; AGND = DGND = 0 V; Reference
Limit at T
MIN
, T
MAX
All Versions
Parameter
Unit
Description
t
1
t
2
t
3
t
4
t
5
t
6
t
6A
t
7
t
8
t
9
t
10
t
11
t
12
25
4.5
25
4.5
25
4.5
6
40
0
40
100
40
100
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Mode Valid to Write Setup Time
Mode Valid to Write Hold Time
Address Valid to Write Setup Time
Address Valid to Write Hold Time
Data Setup Time
Data Hold Time
LDAC
Valid to Write Hold Time
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulsewidth
Time Between Successive Writes
LDAC
,
CLR
Pulsewidth
Write to
LDAC
Setup Time
NOTE
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and
timed from a voltage of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
MODE
CS
WR
DATA
LDAC
2
CLR
LDAC
1
t
1
t
2
t
3
t
4
t
7
t
8
t
9
t
5
t
6
t
10
t
11
t
12
t
11
1
TIMING REQUIREMENTS FOR SYNCHRONOUS
LDAC
UPDATE OR
LDAC
MAY BE TIED PERMANENTLY LOW IF REQUIRED.
2
TIMING REQUIREMENTS FOR ASYNCHRONOUS
LDAC
UPDATE.
t
6A
A0, A1, A2
Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write
相關(guān)PDF資料
PDF描述
AD7805BR %2B3.3V to %2B5V Quad/Octal 10-Bit DACs
AD7805BRS +3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7805CR +3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7808BN +3.3 V to +5 V Quad/Octal 10-Bit DACs
AD7808BR +3.3 V to +5 V Quad/Octal 10-Bit DACs
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