參數(shù)資料
型號(hào)： AD7801BRU
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： +2.7 V to +5.5 V, Parallel Input, Voltage Output 8-Bit DAC
中文描述： PARALLEL, 8 BITS INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDSO20
封裝： TSSOP-20
文件頁數(shù)： 2/16頁
文件大?。?/td> 219K
代理商： AD7801BRU
–2–
REV. 0
AD7801–SPECIFICATIONS
Parameter
(V
DD
= +2.7 V to +5.5 V, Internal Reference; C
L
= 100 pF, R
L
= 10 k
V
to V
DD
and GND.
All specifications T
MN
to T
MAX
unless otherwse noted.)
B Versions
1
Units
Conditions/Comments
ST AT IC PERFORMANCE
Resolution
Relative Accuracy
2
Differential Nonlinearity
Zero-Code Error @ +25
°
C
Full-Scale Error
Zero-Code Error Drift
Gain Error
3
8
±
1
±
1
3
–0.75
100
±
1
Bits
LSB max
LSB max
LSB typ
LSB typ
μ
V/
°
C typ
% FSR typ
Guaranteed Monotonic
All Zeros Loaded to DAC Register
All Ones Loaded to DAC Register
DAC REFERENCE INPUT
REFIN Input Range
REFIN Input Impedance
1 to V
DD
/2
10
V min/V max
M
typ
OUT PUT CHARACT ERIST ICS
Output Voltage Range
Output Voltage Settling T ime
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short Circuit Current
Power Supply Rejection Ratio
4
0 to V
DD
2
7.5
1
0.2
40
14
0.0003
V min/V max
μ
s max
V/
μ
s typ
nV-s typ
nV-s typ
typ
mA typ
%/% max
T ypically 1.2
μ
s
1 LSB Change Around Major Carry
V
DD
=
±
10%
LOGIC INPUT S
Input Current
V
INL
, Input Low Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
V
INH
, Input High Voltage
Pin Capacitance
±
10
0.8
0.6
2.4
2.1
7
μ
A max
V max
V max
V min
V min
pF max
V
DD
= +5 V
V
DD
= +3 V
V
DD
= +5 V
V
DD
= +3 V
POWER REQUIREMENT S
V
DD
I
DD
(Normal Mode)
V
DD
= 3.3 V
@ 25
°
C
T
MIN
to T
MAX
V
DD
= 5.5 V
@ 25
°
C
T
MIN
to T
MAX
I
DD
(Power-Down)
@ 25
°
C
T
MIN
to T
MAX
NOT ES
1
T emperature ranges are as follows: B Version: –40
°
C to +105
°
C
2
Relative Accuracy is calculated using a reduced code range of 15 to 245.
3
Gain Error is specified between Codes 15 and 245. T he actual error at Code 15 is typically 3 LSB.
4
Guaranteed by characterization at product release, not production tested.
Specifications subject to change without notice.
2.7/5.5
V min/V max
DAC Active and Excluding Load Current
V
IH
= V
DD
and V
IL
= GND
See Figure 6
1.55
1.75
mA max
mA max
2.35
2.5
mA max
mA max
1
2
μ
A max
μ
A max
V
IH
= V
DD
and V
IL
= GND
See Figure 18
Figure 1. Timing Diagram for Parallel Data Write
t
1
t
2
t
4
t
3
t
5
t
6
t
7
t
8
CS
WR
D7-D0
LDAC
CLR
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