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參數(shù)資料
| 型號： | AD7791BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Power, Buffered 24-Bit Sigma-Delta ADC |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MSOP-10 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 308K |
| 代理商： | AD7791BRM |
AD7791
ADC CIRCUIT INFORMATION
OVERVIEW
The AD7791 is a low power ADC that incorporates a ∑-
modulator, a buffer and on-chip digital filtering intended for the
measurement of wide dynamic range, low frequency signals
such as those in pressure transducers, weigh scales, and tem-
perature measurement applications.
Rev. 0 | Page 14 of 20
The part has one differential input that can be buffered or
unbuffered. Buffering the input channel means that the part can
accommodate significant source impedances on the analog
input and that R, C filtering (for noise rejection or RFI reduc-
tion) can be placed on the analog input, if required. The device
requires an external reference of 2.5 nominal. Figure 12 shows
the basic connections required to operate the part.
04227-0-006
IN+
10
μ
F
0.1
μ
F
IN–
OUT–
POWER
SUPPLY
OUT+
REFIN(+)
CS
DOUT/RDY
SCLK
V
DD
GND
AIN(+)
AIN(–)
REFIN(–)
AD7791
MICROCONTROLLER
Figure 12. Basic Connection Diagram
The output rate of the AD7791 (f
ADC
) is user programmable
with the settling time equal to 2 × t
ADC
. Normal mode rejection
is the major function of the digital filter. Table 12 lists the avail-
able output rates from the AD7791. Simultaneous 50 Hz and
60 Hz rejection is optimized when the update rate equals
16.6 Hz as notches are placed at both 50 Hz and 60 Hz with this
update rate (see Figure 6).
NOISE PERFORMANCE
Table 13 shows the output rms noise, rms resolution, and peak-
to-peak resolution (rounded to the nearest 0.5 LSB) for the
different update rates and input ranges for the AD7791. The
numbers given are for the bipolar input range with a reference
of 2.5 V. These numbers are typical and generated with a
differential input voltage of 0 V. The peak-to-peak resolution
figures represent the resolution for which there will be no code
flicker within a six-sigma limit. The output noise comes from
two sources. The first is the electrical noise in the semiconduc-
tor devices (device noise) used in the implementation of the
modulator. The second is quantization noise, which is added
when the analog input is converted into the digital domain. The
device noise is at a low level and is independent of frequency.
The quantization noise starts at an even lower level but rises
rapidly with increasing frequency to become the dominant
noise source.
Table 13. Typical Peak-to-Peak Resolution (Effective
Resolution) vs. Update Rate
Update
Rate
Resolution
9.5
19.5
13.3
19
16.7
19
16.6
19
20
18.5
33.3
17.5
100
14.5
120
14
REDUCED CURRENT MODES
The AD7791 has a current consumption of 160 μA maximum
when operated with a 5 V power supply, the buffer enabled, and
the clock operating at its maximum speed. The clock frequency
can be divided by a factor of 2, 4, or 8 before being applied to
the modulator and filter, resulting in a reduction in the current
consumption of the AD7791. Bits CDIV1 and CDIV0 in the
filter register are used to enter these low power modes (see
Table 14).
Peak-toPeak
Effective
Resolution
22
21.5
21.5
21.5
21
20
17
16.5
When the internal clock is reduced, the update rate will also be
reduced. For example, if the filter bits are set to give an update
rate of 16.6 Hz when the AD7791 is operated in full power
mode, the update rate will equal 8.3 Hz in divide by 2 mode. In
the low power modes, there may be some degradation in the
ADC performance.
Table 14. Low Power Mode Selection
CDIV[1:0]
Clock
00
1
10
1/2
10
1/4
11
1/8
Typ Current, Buffered (μA)
146
87
56
41
Typ Current, Unbuffered (μA)
75
45
30
25
50 Hz/60 Hz Rejection (dB)
65
64
75
86
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