參數(shù)資料
型號: AD7789BRM
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: Low Power, 16-/24-Bit Sigma-Delta ADC
中文描述: 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10
封裝: MO-187BA, MSOP-10
文件頁數(shù): 15/20頁
文件大?。?/td> 288K
代理商: AD7789BRM
AD7788/AD7789
The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/RDY lines are used to
communicate with the AD7788/AD7789. The end of conversion
can be monitored using the RDY bit in the status register. This
scheme is suitable for interfacing to microcontrollers. If CS is
required as a decoding signal, it can be generated from a port
pin. For microcontroller interfaces, it is recommended that
SCLK idles high between data transfers.
Rev. 0 | Page 15 of 20
The AD7788/AD7789 can be operated with CS being used as a
frame synchronization signal. This scheme is useful for DSP
interfaces. In this case, the first bit (MSB) is effectively clocked
out by CS since CS would normally occur after the falling edge
of SCLK in DSPs. The SCLK can continue to run between data
transfers, provided the timing numbers are obeyed.
The serial interface can be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the AD7788/AD7789 line
for at least 32 serial clock cycles, the serial interface is reset. This
ensures that in 3-wire systems, the interface can be reset to a
known state if the interface gets lost due to a software error or
some glitch in the system. Reset returns the interface to the state
in which it is expecting a write to the communications register.
This operation resets the contents of all registers to their power-
on values.
The AD7788/AD7789 can be configured to continuously con-
vert or to perform a single conversion. See Figure 11 through
Figure 13.
Single Conversion Mode
In single conversion mode, the AD7788/AD7789 is placed in
shutdown mode between conversions. When a single conver-
sion is initiated by setting MD1 to 1 and MD0 to 0 in the mode
register, the AD7788/AD7789 powers up, performs a single con-
version, and then returns to shutdown mode. A conversion will
require a time period of 2 × t
ADC
. DOUT/RDY goes low to indi-
cate the completion of a conversion. When the data-word has
been read from the data register, DOUT/RDY will go high. If CS
is low, DOUT/RDY will remain high until another conversion is
initiated and completed. The data register can be read several
times, if required, even when DOUT/ RDY has gone high.
Continuous Conversion Mode
This is the default power-up mode. The AD7788/AD7789 will
continuously convert, the RDY pin in the status register going
low each time a conversion is complete. If CS is low, the
DOUT/RDY line will also go low when a conversion is
complete. To read a conversion, the user can write to the
communications register, indicating that the next operation is a
read of the data register. The digital conversion will be placed
on the DOUT/RDY pin as soon as SCLK pulses are applied to
the ADC. DOUT/RDY will return high when the conversion is
read. The user can read this register additional times, if
required. However, the user must ensure that the data register is
not being accessed at the completion of the next conversion or
else the new conversion word will be lost.
03539-0-010
DIN
0x10
0x82
0x10
0x82
DATA
DATA
SCLK
DOUT/RDY
CS
Figure 11. Single Conversion
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AD7788BRM Low Power, 16-/24-Bit Sigma-Delta ADC
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