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參數(shù)資料
| 型號： | AD7787BRM-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Power, 2-Channel 24-Bit Sigma-Delta ADC |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 326K |
| 代理商： | AD7787BRM-REEL |
AD7787
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 8 of 20
0
AD7787
TOP VIEW
(Not to Scale)
SCLK
1
CS
2
AIN1(+)
3
AIN1(–)
4
REFIN
5
DIN
DOUT/RDY
V
DD
GND
AIN2
10
9
8
7
6
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
Mnemonic Function
1
SCLK
Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the
interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a
continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or
from the ADC in smaller batches of data.
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems
with more than one device on the serial bus or as a frame synchronization signal in communicating with the device.
CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface
with the device.
Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1().
Analog Input. AIN1() is the negative terminal of the differential analog input pair AIN1(+)/AIN1().
Reference Input. REFIN can be anywhere between V
DD
and GND + 0.1 V. The nominal reference voltage is 2.5 V, but
the part functions with a reference from 0.1 V to V
DD
.
Analog Input. AIN2 is a single-ended analog input.
Ground Reference Point.
Supply Voltage, 2.5 V to 5.25 V.
DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to
access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or
control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a
conversion. If the data is not read after the conversion, the pin will go high before the next update occurs.
The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an
external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is
placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.
The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY pin is
three-stated, but the RDY bit remains active.
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers
within the ADC; the register selection bits of the communications register identifying the appropriate register.
2
CS
3
4
5
AIN1(+)
AIN1(–)
REFIN
6
7
8
9
AIN2
GND
V
DD
10
DIN
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