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參數(shù)資料
| 型號： | AD7783BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Read-Only, Pin Configured 24-Bit ADC with Excitation Current Sources |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MS-153-AB, TSSOP-16 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 217K |
| 代理商： | AD7783BRU |
REV. B
–4–
AD7783
TIMING CHARACTERISTICS
1, 2
Input Logic 0 = 0 V, Logic 1 = V
DD
, unless otherwise noted.)
Limit at T
MIN
, T
MAX
(B Version)
Parameter
Unit
m
s typ
ms typ
ns min
ns max
ns max
ns typ
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
Conditions/Comments
t
1
t
ADC
t
2
30.5176
50.54
0
60
80
2
￥
t
ADC
0
60
80
10
80
0
10
80
Crystal Oscillator Period
19.79 Hz Update Rate
CS
Falling Edge to DOUT Active
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
Channel Settling Time
SCLK Active Edge to Data Valid Delay
4
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
Bus Relinquish Time after
CS
Inactive Edge
t
3
t
43
t
75
t
8
t
9
CS
Rising Edge to SCLK Inactive Edge Hold Time
SCLK Inactive to DOUT High
Slave Mode Timing
t
5
t
6
Master Mode Timing
t
5
t
6
t
10
100
100
ns min
ns min
SCLK High Pulse Width
SCLK Low Pulse Width
t
1
/2
t
1
/2
t
1
/2
3t
1
/2
m
s typ
m
s typ
m
s min
m
s max
SCLK High Pulse Width
SCLK Low Pulse Width
DOUT Low to First SCLK Active Edge
4
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 2.
3
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin-
quish times of the part and as such are independent of external bus loading capacitances.
(V
DD
= 2.7 V to 3.6 V or V
DD
= 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz;
TO OUTPUT
PIN
50pF
I
(1.6mA WITH V
DD
= 5V
100 A WITH V
DD
= 3V)
1.6V
I
(200 A WITH V
DD
= 5V
100 A WITH V
DD
= 3V)
Figure 1. Load Circuit for Timing Characterization
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