參數(shù)資料
型號(hào): AD7782BRUZ-REEL7
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 10/12頁(yè)
文件大?。?/td> 0K
描述: IC ADC 24BIT 2CHAN 16TSSOP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 24
采樣率(每秒): 19.79
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 3.9mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 2 個(gè)差分,單極;2 個(gè)差分,雙極
AD7782
–7–
Typical Performance Characteristics
8
7
0
8388039
8388721
8388687
8388657
8388615
8388579
8388547
8388499
8388449
8388382
8388754
8389110
8389033
8388985
8388941
8388906
8388874
8388841
8388805
8388779
6
5
4
3
2
1
9
TPC 1. Noise Distribution Histogram
ADC CIRCUIT INFORMATION
Overview
The AD7782 incorporates an analog multiplexer with a
Σ- ADC
channel, on-chip programmable gain amplifier, and on-chip digital
filtering intended for the measurement of wide dynamic range,
low-frequency signals such as those in weigh-scale, strain-gage,
pressure transducer, or temperature measurement applications.
This ADC input is buffered and can be programmed to have an
input voltage range of
±160 mV or ±2.56 V. The input channels
are configured as two fully differential inputs. Buffering the input
channels means that the part can accommodate significant source
impedances on the analog inputs and that R, C filtering (for
noise rejection or RFI reduction) can be placed on the analog
inputs if required. The device requires an external reference of
+2.5 V nominal. Figure 3 shows the basic connections required
to operate the part.
AD7782
REFIN(+)
REFIN(–)
AIN1(–)
AIN1(+)
AIN2(–)
AIN2(+)
XTAL1
XTAL2
VDD
DOUT/
RDY
CS
SCLK
GND
POWER
SUPPLY
10 F
0.1 F
CONTROLLER
32.768kHz
CRYSTAL
6k
10k
IN–
OUT+
OUT–
IN+
Figure 3. Basic Connection Diagram
The output rate of the AD7782 (fADC) equals:
fADC
× ×
()
32 768
10
69
8
3
./
while the settling time equals:
t
f
t
SETTLE
ADC
=
2
Normal-mode rejection is the major function of the digital filter on
the AD7782. Simultaneous 50 Hz and 60 Hz rejection of better
than 60 dB is achieved as notches are placed at both 50 Hz and
60 Hz. Figure 4 shows the filter rejection.
FREQUENCY – Hz
0
10
406080
100
A
TTENU
A
TION
dB
–40
–80
–120
–140
–160
–20
–60
–100
20
30
50
70
90
OUTPUT DATA RATE = 19.8Hz
INPUT BANDWIDTH = 4.74Hz
50Hz REJECTION = –66dB, 50Hz
1Hz REJECTION = –60dB
60Hz REJECTION = –117dB, 60Hz
1Hz REJECTION = –94dB
Figure 4. Filter Profile (Filter Notches at
Both 50 Hz and 60 Hz)
2.5
0
1.0
3.0
2.5
2.0
1.5
3.5
5.0
4.5
4.0
2.0
1.5
1.0
0.5
3.0
VREF – V
RMS
NOISE
V
160mV RANGE
2.56V RANGE
VDD = 5V
VREF = 2.5V
TA = 25 C
TPC 2. RMS Noise vs. Reference Input
REV. A
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