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參數(shù)資料
| 型號： | AD7781BRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 20BIT 1CH LP SD 14SOIC |
| 產(chǎn)品培訓模塊： | Weigh Scale Introduction |
| 設(shè)計資源： | Weigh Scale Design Using AD7781 with Internal PGA (CN0108) |
| 標準包裝： | 56 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 16.7 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SO |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 779 (CN2011-ZH PDF) |
AD7781
Rev. 0 | Page 14 of 16
APPLICATIONS INFORMATION
The AD7781 provides a low cost, high resolution analog-to-
digital function. Because the analog-to-digital function is
provided by a Σ-Δ architecture, the part is more immune to
noisy environments, making it ideal for use in sensor measure-
ment and industrial and process control applications.
WEIGH SCALES
Figure 23 shows the AD7781 being used in a weigh scale
application. The load cell is arranged in a bridge network and
gives a differential output voltage between its OUT+ and OUT
terminals. Assuming a 5 V excitation voltage, the full-scale
output range from the transducer is 10 mV when the sensitivity
is 2 mV/V. The excitation voltage for the bridge can be used to
directly provide the reference for the ADC because the refer-
ence input range includes the supply voltage.
A second advantage of using the AD7781 in transducer-based
applications is that the bridge power-down switch (BPDSW)
can be fully utilized in low power applications. The bridge power-
down switch is connected in series with the low side of the bridge.
In normal operation, the switch is closed and measurements
can be taken. In applications where power is of concern, the
AD7781 can be placed in power-down mode, significantly
reducing the power consumed in the application. In addition,
the bridge power-down switch is opened while in power-down
mode, thus avoiding unnecessary power consumption by the
front-end transducer. When the part is taken out of power-down
mode and the bridge power-down switch is closed, the user should
ensure that the front-end circuitry is fully settled before attempting
to read from the AD7781.
The load cell has an offset, or tare, associated with it. This tare is
the main component of the system offset (load cell + ADC) and
is similar in magnitude to the full-scale signal from the load cell.
For this reason, calibrating the offset and gain of the AD7781
alone is not sufficient for optimum accuracy; a system calibration
that calibrates the offset and gain of the ADC, plus the load cell,
is required. A microprocessor can be used to perform the calibra-
tions. The offset error (the conversion result from the AD7781
when no load is applied to the load cell) and the full-scale error
(the conversion result from the ADC when the maximum load
is applied to the load cell) must be determined. Subsequent
conversions from the AD7781 are then corrected, using the
offset and gain coefficients that were calculated from these
calibrations.
AD7781 PERFORMANCE IN A WEIGH SCALE SYSTEM
If the load cell has a sensitivity of 2 mV/V and a 5 V excitation
voltage is used, the full-scale signal from the load cell is 10 mV.
When the AD7781 (C grade) operates with a 10 Hz output data
rate and the gain is set to 128, the device has a p-p resolution of
18.2 bits when the reference is equal to 5 V. Postprocessing the
data from the AD7781 using a microprocessor increases the p-p
resolution. For example, an average by 4 in the microprocessor
increases the accuracy by 2 bits. The noise-free counts value is
equal to
Noise-Free Counts = (2Effective Bits) × (FSLC/FSADC)
where:
Effective Bits = 18.2 bits (AD7781) + 2 bits (due to postprocessing
in the microprocessor).
FSLC is the full-scale signal from the load cell (10 mV).
FSADC is the full-scale input range when gain = 128 and
VREF = 5 V (78 mV).
The noise-free counts is equal to
(218.2 + 2) × (10 mV/78 mV) = 154,422
This example shows that with a 5 V supply, 154,422 noise-free
counts can be achieved with the AD7781.
EMI RECOMMENDATIONS
For simplicity, the EMI filters are not included in Figure 23.
However, an R-C antialiasing filter should be included on each
analog input. This filter is needed because the on-chip digital
filter does not provide any rejection around the master clock or
multiples of the master clock. Suitable values are a 1 kΩ resistor
in series with each analog input, a 0.1 μF capacitor from AIN(+)
to AIN(), and 0.01 μF capacitors from AIN(+)/AIN() to GND.
G = 1
OR 128
20-BIT Σ-Δ
ADC
DOUT/RDY
GND
AVDD
AIN(+)
REFIN(+)
AIN(–)
SCLK
DVDD
FILTER
GAIN
INTERNAL
CLOCK
AD7781
PDRST
BPDSW
REFIN(–)
VDD
OUT–
IN+
IN–
OUT+
81
62
-02
3
0
Figure 23. Weigh Scales Using the AD7781
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| AD7781BRZ | 制造商:Analog Devices 功能描述:IC ADC 20BIT 16.7SPS SOIC-14 |
| AD7781BRZ-REEL | 功能描述:IC ADC 20BIT 1CH LP SD 14SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個單端，雙極；8 個差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
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