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參數(shù)資料
| 型號： | AD7777AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCs |
| 中文描述： | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | MS-013AE, SOIC-28 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 220K |
| 代理商： | AD7777AR |
AD7776/AD7777/AD7778
–3–
REV. 0
TIMNGSPECIFICATIONS
1, 2
(V
CC
= +5 V
6
5%; AGND = DGND = 0 V; all specifications T
MN
to T
MAX
unless otherwse noted.)
t
3
t
11
t
10
t
9
t
8
FIRST
CONVERSION
FINISHED
(CR6 = 0)
SECOND
CONVERSION
FINISHED (CR6 = 1)
AD7777/AD7778 ONLY
t
9
BUSY
(CR8 = 0)
INT
(CR8 = 1)
t
10
WR, RD
Figure 3.
BUSY
/
INT
Timing
I
OL
1.6mA
+2.1V
I
OH
200
μ
A
C
OUT
100pF
DB n
Figure 4. Load Circuit for Bus Timing Characteristics
t
1
CS
t
2
t
4
t
5
RD
DB0–DB9
Figure 1. Read Cycle Timing
t
1
CS
t
2
t
6
WR
DB0–DB9
t
3
t
7
Figure 2. Write Cycle Timing
Parameter
Label
Limit at T
MIN
to T
MAX
Units
T est Conditions/Comments
INT ERFACE T IMING
CS
Falling Edge to
WR
or
RD
Falling Edge
WR
or
RD
Rising Edge to
CS
Rising Edge
WR
Pulse Width
CS
or
RD
Active to Valid Data
3
Bus Relinquish T ime after
RD
4
t
1
t
2
t
3
t
4
t
5
0
0
53
60
10
45
55
10
1.5 t
CLK IN
2.5 t
CLK IN
+ 70
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns max
T imed from Whichever Occurs Last
Data Valid to
WR
Rising Edge
Data Valid after
WR
Rising Edge
WR
Rising Edge to
BUSY
Falling Edge
t
6
t
7
t
8
CR9 = 0
WR
Rising Edge to
BUSY
Rising Edge or
INT
Falling Edge
t
9
t
10
t
11
19.5 t
CLK IN
+ 70
33.5 t
CLK IN
+ 70
60
ns max
ns max
ns max
Single Conversion, CR6 = 0
Double Conversion, CR6 = 1
CR9 = 1
WR
or
RD
Falling Edge to
INT
Rising Edge
NOT ES
1
See Figures 1 to 3.
2
T iming specifications in
bold
print are 100% production tested. All other times are guaranteed by design, not production tested. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3
t
4
is measured with the load circuit of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. T he measured time is then extrapolated back
to remove the effects of charging or discharging the 100 pF capacitor. T his means that the time t
5
quoted above is the true bus relinquish time of the device and, as
such, is independent of the external bus loading capacitance.
Specifications subject to change without notice.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7777AR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 378ksps 10-bit Parallel 28-Pin SOIC W T/R |
| AD7777ARZ | 功能描述:IC ADC 10BIT 4CH HS 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7777ARZ-REEL | 功能描述:IC ADC 10BIT 4CHAN HS 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7778 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS, High Speed 1-, 4- & 8-Channel 10-Bit ADCs |
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