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參數(shù)資料
| 型號： | AD7769 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LC2MOS Analog I/O Port |
| 中文描述： | LC2MOS模擬I / O端口 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 265K |
| 代理商： | AD7769 |
DACA, DACB SPECIFICATIONS
Parameter
(V
DD
= +12 V
6
10%; V
CC
= +5 V
6
5%; AGND [DAC] = AGND [ADC] = DGND = 0 V;
V
BIAS
[DAC] = +5 V; V
SWING
[DAC] = +2.5 V; V
OUT
A, V
OUT
B load to AGND [DAC], R
L
= 5 k
V
,
C
L
= 100 pF. All specifications T
MN
to T
MAX1
unless otherwse noted.)
J Version
A Version Units
Conditions/Comments
ST AT IC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
+25
°
C
T
MIN
to T
MAX
Bias Offset Match
+25
°
C
T
MIN
to T
MAX
Plus or Minus Full-Scale Error
+25
°
C
T
MIN
to T
MAX
Plus or Minus Full-Scale Match
+25
°
C
T
MIN
to T
MAX
ADC to DAC MAT CHING
DYNAMIC PERFORMANCE
2
Signal-to-Noise Ratio (SNR)
T otal Harmonic Distortion (T HD)
Intermodulation Distortion (IMD)
8
±
1
±
1
*
*
*
Bits
LSB max
LSB max
See T erminology
Guaranteed Monotonic. See T erminology.
See T erminology
±
2.0
±
2.5
*
*
LSB max
LSB max
V
OUT
A to V
OUT
B
±
2.5
±
3.5
*
*
LSB max
LSB max
See T erminology
±
1.5
±
2.0
*
*
LSB max
LSB max
V
OUT
A to V
OUT
B
±
3.5
±
4.0
*
*
LSB max
LSB max
As Per ADC Specifications
44
48
55
*
*
*
dB min
dB max
dB typ
V
OUT
= 20 kHz Full-Scale Sine Wave With f
SAMPLING
= 400 kHz
V
OUT
= 20 kHz Full-Scale Sine Wave With f
SAMPLING
= 400 kHz
f
a
= 18.4 kHz, f
b
= 14.5 kHz with f
SAMPLING
= 400 kHz
ANALOG OUT PUT S
Output Voltage Ranges
V
OUT
A, V
OUT
B
V
BIAS
– V
SWING
or 0.5
V
BIAS
+ V
SWING
or
V
DD
–2.0
0.5
20
V min
Whichever Is the Higher
V max
typ
mA typ
Whichever Is the Lower
DC Output Impedance
Short-Circuit Current
*
*
DAC REFERENCE INPUT S
Input Voltage Levels
V
BIAS
(DAC)
V
SWING
(DAC)
Input Currents
V
BIAS
(DAC) Input
V
SWING
(DAC) Input
AC CHARACT ERIST ICS
2
Voltage Output Settling T ime
Digital-to-Analog Glitch Impulse
Digital Feedthrough
3/6.8
2.0/3.0
*
*
V min/max With Respect to AGND (DAC). For Specified Performance.
V min/max With Respect to AGND (DAC). For Specified Performance.
±
2
±
1
*
*
μ
A max
μ
A max
4
30
1
*
*
*
μ
s max
nV sec typ
nV sec typ
Settling T ime to Within
±
1/2 LSB of Final Value. T ypically 2.5
μ
s.
See T erminology
See T erminology
LOGIC INPUT S
CS
,
RD
,
WR
,
ADC
/DAC,
CHA
/CHB, DB0–DB7
Input Low Voltage, V
INL
Input High Voltage, V
INH
Input Leakage Current
Input Capacitance
CLK
Input Low Voltage
Input High Voltage
Input Leakage Current
DB0–DB7
Input Coding
0.8
2.4
±
10
10
*
*
*
*
V max
V min
μ
A max
pF max
0.8
2.4
±
10
*
*
*
V max
V min
μ
A max
External Clock. For Internal Clock Operation Connect
the CLK Pin to V
DD
.
Offset Binary
POWER REQUIREMENT S
As per ADC Specifications
NOT ES
1
T emperature range as follows: J Version: 0
°
C to +70
°
C; A Version: –40
°
C to +85
°
C.
2
Sample tested at +25
°
C to ensure compliance.
*Specifications same as J Version.
Specifications subject to change without notice.
–3–
REV. A
AD7769
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PDF描述 |
|---|---|
| AD7769AN | LC2MOS Analog I/O Port |
| AD7769AP | LC2MOS Analog I/O Port |
| AD7769JN | LC2MOS Analog I/O Port |
| AD7769JP | LC2MOS Analog I/O Port |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7769AN | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Analog I/O Port |
| AD7769AP | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Analog I/O Port |
| AD7769JN | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Analog I/O Port |
| AD7769JP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD7769JP-REEL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
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