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參數(shù)資料
| 型號： | AD7760 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2.5 MSPS, 20-Bit ADC |
| 中文描述： | 2.5 MSPS的20位ADC |
| 文件頁數(shù)： | 14/22頁 |
| 文件大?。?/td> | 868K |
| 代理商： | AD7760 |
AD7760
Preliminary Technical Data
CLOCKING THE AD7760
The AD7760 requires an external low jitter clock source. This
signal is applied to the MCLK and MCLK pins. An internal
clock signal (ICLK) is derived from the MCLK input signal.
This ICLK controls all the internal operation of the AD7760.
The maximum ICLK frequency is 20MHz but due to an internal
clock divider, a range of MCLK frequencies can be used. There
are three possibilities available to generate the ICLK:
Rev. PrN | Page 14 of 22
1.
ICLK = MCLK (CDIV[1:0] = 10)
2.
ICLK = MCLK / 2 (CDIV[1:0] = 00)
3.
ICLK = MCLK / 4 (CDIV[1:0] = 01)
These options are selected from the control register (See
Register Section for further details). On power-up, the default is
ICLK = MCLK / 4 to ensure that the part can handle the
maximum MCLK frequency of 80MHz. If the user wishes to get
output data rates equal to those used in audio systems, a 12.288
MHz ICLK frequency can be used. As shown in Table 5, output
data rates of 192, 96 and 48kHz are achievable with this ICLK
frequency. As mentioned previously, this ICLK frequency can
be derived from different MCLK frequencies.
The MCLK jitter requirements depend on a number of factors
and are given by the following equation:
20
)
(
)
(
10
2
dB
SNR
IN
RMS
j
f
OSR
t
×
×
×
=
π
OSR = Over-sampling ratio =
ODR
f
ICLK
f
IN
= Maximum Input Frequency
SNR(dB) = Target SNR.
Taking an example from Table 5:
ODR = 2.5MHz,
f
ICLK
= 20MHz,
f
IN
(max) = 1MHz, SNR =
108dB
ps
t
RMS
j
79
.
10
10
2
8
4
6
)
(
=
×
×
×
=
π
This is the maximum allowable clock jitter for a full-scale
1MHz input tone with the given ICLK and Output Data Rate.
Taking a second example from Table 5:
ODR = 48kHz,
f
ICLK
= 12.288MHz,
f
IN
(max) = 19.2kHz, SNR =
120dB
ps
t
RMS
j
133
10
10
2
19
2
256
×
6
3
)
(
=
×
×
×
=
π
The input amplitude also has an effect on these jitter figures. If,
for example, the input level was 3dB down from full-scale, the
allowable jitter would be increased by a factor of √2 increasing
the first example to 2.53ps RMS. This is due to the fact that the
maximum slew rate is reduced by a reduction in amplitude.
Figure 14 and Figure 15 illustrate this point showing the
maximum slew rate of a sine wave of the same frequency but
with different amplitudes.
Figure 14. Maximum Slew Rate of Sine Wave with Amplitude of 2V Pk-Pk
Figure 15. Maximum Slew Rate of Same Frequency Sine Wave with
Amplitude of 1V Pk-Pk
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| AD7760BSVZ | 功能描述:IC ADC 24BIT 2.5MSPS 64TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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