參數(shù)資料
型號(hào): AD7755ABRS
廠商: ANALOG DEVICES INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: Energy Metering IC with Pulse Output
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: SSOP-24
文件頁數(shù): 12/16頁
文件大?。?/td> 250K
代理商: AD7755ABRS
REV. B
AD7755
–12–
Figure 25 shows two typical connections for Channel V2. The
first option uses a PT (potential transformer) to provide com-
plete isolation from the mains voltage. In the second option the
AD7755 is biased around the neutral wire, and a resistor divider
is used to provide a voltage signal that is proportional to the line
voltage. Adjusting the ratio of Ra, Rb and VR is also a conve-
nient way of carrying out a gain calibration on the meter.
660mV
Ra
*
Rb
*
VR
*
V2P
AGND
Rf
Rf
CT
NEUTRAL
PHASE
V2N
Cf
Cf
660mV
V2P
Rf
NEUTRAL
PHASE
V2N
Cf
Cf
*
Ra >> Rb + VR
*
Rb + VR = Rf
Figure 25. Typical Connections for Channel 2
POWER SUPPLY MONITOR
The AD7755 contains an on-chip power supply monitor. The
Analog Supply (AV
DD
) is continuously monitored by the AD7755.
If the supply is less than 4 V
±
5%, the AD7755 will be reset.
This is useful to ensure correct device start-up at power-up and
power-down. The power supply monitor has built in hysteresis
and filtering. This gives a high degree of immunity to false trig-
gering due to noisy supplies.
As can be seen from Figure 26, the trigger level is nominally set
at 4 V. The tolerance on this trigger level is about
±
5%. The
power supply and decoupling for the part should be such that
the ripple at AV
DD
does not exceed 5 V
±
5% as specified for
normal operation.
AV
DD
5V
4V
0V
INTERNAL
RESET
RESET
TIME
ACTIVE
RESET
Figure 26. On-Chip Power Supply Monitor
HPF and Offset Effects
Figure 27 shows the effect of offsets on the real power calcula-
tion. As can be seen, an offset on Channel 1 and Channel 2 will
contribute a dc component after multiplication. Since this dc
component is extracted by the LPF and used to generate the
real power information, the offsets will have contributed a con-
stant error to the real power calculation. This problem is easily
avoided by enabling the HPF (i.e., pin AC/
DC
is set logic high)
in Channel 1. By removing the offset from at least one channel,
no error component can be generated at dc by the multiplica-
tion. Error terms at cos(
ω
t) are removed by the LPF and the
digital-to-frequency conversion—see Digital-to-Frequency
Conversion section.
V
{
t
V
I
t
I
V
I
V
I
V
I
t
I
V
t
V
I
t
OS
OS
OS
OS
OS
OS
cos
cos
cos
cos
cos
ω
( )
+
ω
ω
( )
+
ω
ω
}
×
( )
+
{
}
=
×
2
+
×
+
×
×
( )
+
×
2
×
(
)
2
V
OS
I
OS
I
OS
V
V
OS
I
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
2
FREQUENCY
RAD/S
2
V I
0
Figure 27. Effect of Channel Offset on the Real Power
Calculation
The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figures 28 and 29 show the phase error between
channels with the compensation network activated. The AD7755
is phase compensated up to 1 kHz as shown. This will ensure
correct active harmonic power calculation even at low power
factors.
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