
PRELIMINARY TECHNICAL DATA
AD7755
9
PRELIM B2 10/98
THEORY OF OPERATION
The two ADCs digitize the voltage signals from the current and
voltage transducers. These ADCs are 16 bit second order sigma
delta with an over sampling rate of 900kHz. This analog input
structure greatly simplifies transducer interfacing by providing a
wide dynamic range for direct connection to the transducer and
also simplifying the antialiasing filter design. A programmable
gain stage in the current channel further facilitates easy
transducer interfacing. A high pass filter in the current channel
removes any dc component from the current signal. This
eliminates any inaccuracies in the real power calculation due to
offsets in the voltage or current signals.
The real power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals. In order
to extract the real power component (i.e., the dc component)
the instantaneous power signal is low pass filtered. Figure 5
illustrates the instantaneous real power signal and shows how
the real power information can be extracted by low pass
filtering the instantaneous power signal. This scheme calculates
real power correctly for non sinusoidal current and voltage
waveforms at all power factors. All signal processing is carried
out in the digital domain for superior stability over temperature
and time.
The low frequency output of the AD7755 is generated by
accumulating this real power information. This low frequency
inherently means a long accumulation time between output
pulses. The output frequency is therefore proportional to the
average real power. This average real power information can in
turn be accumulated (e.g., by a counter) to generate real energy
information. Because of its high output frequency and hence
shorter integration time, the CF output is proportional to the
instantaneous real power. This is useful for system calibration
purposes which would take place under steady load conditions.
Figure 5. AD7755 Signal Processing Block Diagram
Offset Effects
Figure 6 shows the effect of offsets on the real power calcula-
tion. As can be seen from figure 2 an offset on Channel 1 and
Channel 2 will contribute a dc component after multiplication.
Since this dc component is extracted by the LPF to generate
the real power information, the offsets will have contributed an
error to the real power calculation. This problem is easily
avoided by enabling the HPF (i.e., pin AC/
DC
is set logic high)
in Channel 1. By removing the offset from at least 1 channel no
error component can be generated at dc by the multiplication.
Error terms at Cos(
ω
.t) are removed by the LPF.
Figure 6. Effect of channel offsets on the real
power calculation
MULTIPLIER
ADC
HPF
LPF
Σ
Σ
DIGITAL TO
FREQUENCY
F1
F2
CF
CH1
CH2
V.I
2
time
V.I
Instantaneous Power Signal - p(t)
Instantaneous Real Power Signal
p(t) = i(t).v(t)
{
1 cos(2. .t)
}
where:
v(t) = V.cos( .t)
i(t) = I.cos( .t)
V.I
2
p(t) =
V.I
2
ADC
PGA
V.I
2
frequency (rad/s)
ω
2
ω
0
VOS.IOS
VOS.I
IOS.V
DC component (including error term) is
extracted by the LPF for real power
calculation