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參數(shù)資料
| 型號： | AD7750 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Product-to-Frequency Converter(乘積-頻率轉換器) |
| 中文描述： | 產(chǎn)品頻率轉換器（乘積-頻率轉換器） |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 155K |
| 代理商： | AD7750 |
AD7750
–14–
REV. 0
Registering the Power Output
T he low frequency pulse outputs (F1 and F2) of the AD7750
provide the frequency output from the product-to-frequency
conversion. T hese outputs can be used to drive a stepper motor
or impulse counter.
A high frequency output is available at the pin F
OUT
. T his high
frequency output is used for calibration purposes. In Mode 2
the output frequency is 16
×
F1(2). With a load current of Ib
the frequency at F
OUT
will be 1.4656 Hz (0.0916 Hz
×
16 from
calculations). If a higher frequency output is required, the FS
pin can be set to V
DD
5 V for calibration. In this case the output
frequency is equal to 64
×
F1 or 5.8624 Hz at Ib—see T able I.
NO LOAD T HRE SHOLD OF T HE AD7750
T he AD7750 will detect when the power drops below a certain
level. When the power (current) drops below a predefined
threshold the AD7750 will cease to generate an output drive for
the stepper motor (F1, F2). T his feature of the AD7750 is
intended to reproduce the behavior of Ferraris meters. A
Ferraris meter will have friction associated with the wheel rota-
tion, therefore the wheel will not rotate below a certain power
level. T he no load threshold is only implemented in the Magni-
tude Only modes (Modes 1, 2, 5 and 6—see T able I). T he
IEC1036 specification includes a test for this effect by requiring
no output pulses during some predetermined time period. T his
time period is calculated as:
time period =
60,000
/pulses-per-minute
If a meter is calibrated to 100 PPK WHR with a F
OUT
running
16 times faster than F1 and F2, this time period is 37.5 minutes
(60,000/1,600). T he IEC1036 specifications state that the no
load threshold must be less than the start up current level. T his
is specified as 0.4% of Ib.
T he threshold level for a given design can be easily calculated
given that the minimum output frequency of the AD7750 is
0.00048% of the maximum output frequency for a full-scale
differential dc input. For example if FS = 0, the maximum
output frequency for a full-scale dc input is 2.9 Hz (see T able II)
and the minimum output frequency is, therefore, 1.39
×
10
–5
Hz.
Calculating the T hreshold Power (Current)
T he meter used in this example is calibrated to 100 PPK WHR,
has an Ib (basic current) of 15 A rms, the line voltage is 220 V
rms and the turns ratio of the CT on Channel 1 is 120:1 with an
2
shunt resistor.
T he nominal voltage on Channel 2 of the AD7750 is 255 mV
rms. An F
MAX
of 6.8 Hz is selected by setting FS = 0. A Magni-
tude Only Mode (Mode 2) is selected to enable the no load thresh-
old. T he gain on Channel 1 is set to 1. T he threshold power or
current can be found by using the transfer function in T able I.
F1, F2 = (1.32
×
V
1
×
V
2
×
Gain
×
F
MAX
)/V
REF
From the transfer function V
1
is calculated as 37.95
μ
V rms—
see Calculation 3.
2
T his is equivalent to a line current of:
(37.95
μ
V/
2
)
×
120
=
2.27
mA rms or
0.5
W
or
(2.27
mA/
15
A)
×
100%
=
0.015% of
Ib
.
NOT E: T he no load threshold as a percentage of Ib will be
different for each value of Ib since the no load in watts is fixed:
FS = 0, the no load threshold is (F
MAX
= 6.8 Hz)
0.5 Watts for a 100 PPK WHR meter
5 Watts for a 10 PPK WHR meter
FS = 1, the no load threshold is (F
MAX
= 13.6 Hz)
1 Watt for a 100 PPK WHR meter
10 Watts for a 10 PPK WHR meter
Calculation 3
F
MIN
= 1.32
×
V
1
×
V
2
×
Gain
×
6.8 Hz) V
REF2
1.39
×
10–5 Hz = V
1
×
0.2555
×
1
×
6.8)/6.25
V
1
= 37.95
μ
V
E X T E RNAL LE AD/LAG COMPE NSAT ION
External phase compensation is often required in a power meter
design to eliminate the phase errors introduced by transducers
and external components. T he design restriction on any external
compensating network is that the network must have an overall
low-pass response with a 3 dB point located somewhere between
5 kHz and 6 kHz. T he corner frequency of this LPF(s) is much
higher than the band of interest. T he reason for this is to mini-
mize its effect on phase variation at 50 Hz due to component
tolerances.
With the antialiasing filters on all channels having the same
corner (–3 dB) frequency, the main contribution to phase error
will be due to the CT . A phase lead in a channel is compensated
by lowering the corner frequency of the antialiasing filter to
increase its associated lag and therefore cancel the lead. A phase
lag in a channel should be compensated by introducing extra lag
in the other channel. T his can be done as previously described,
i.e., moving the corner frequency of the antialiasing filters. T he
result in this case is that the signal on both channels has the
same amount of phase lag and is therefore in phase at the analog
inputs to the AD7750. T he recommended RC values for the
antialiasing filters on the voltage and current channels (see
Antialiasing Components Channels 1 and 2) are R = 1 k
,
C = 33 nF and R = 100
, C = 330 nF respectively. T hese
values produce a phase lag of 0.6
°
through the filters. Varying R
in the antialiasing network from 80
to 100
or 800
to 1 k
produces a phase variation from 0.475
°
to 0.6
°
at 50 Hz. T his
allows the user to vary the lag by 0.125
°
.
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