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參數(shù)資料
| 型號： | AD7739BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, High Throughput, 24-Bit Sigma-Delta ADC |
| 中文描述： | 8-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-153AD, TSSOP-24 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大小： | 380K |
| 代理商： | AD7739BRU |
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AD7739
Parameter
POWER REQUIREMENTS
AV
DD
to AGND Voltage
DV
DD
to DGND Voltage
AV
DD
Current (Normal Mode)
AV
DD
Current (Reduced Power Mode)
AV
DD
Current (Internal Buffer Off)
DV
DD
Current (Normal Mode)
13
DV
DD
Current (Normal Mode)
13
Power Dissipation (Normal Mode)
13
Power Dissipation
(Reduced Power Mode)
13
Power Dissipation
(Reduced Power Mode)
13
AV
DD
+ DV
DD
Current
(Standby Mode)
14
Power Dissipation (Standby Mode)
14
Rev. 0 | Page 5 of 32
Min
4.75
4.75
2.70
Typ
13.6
9.2
8.5
2.7
1.0
85
60
Max
5.25
5.25
3.60
16
11
3
1.5
100
70
Unit
V
V
V
mA
mA
mA
mA
mA
mW
mW
Test Conditions/Comments
MCLK = 4 MHz
DV
DD
= 5 V
DV
DD
= 3 V
DV
DD
= 5 V, MCLK = 4 MHz
50
mW
DV
DD
= 3 V, MCLK = 4 MHz
80
μA
500
μW
1
Specification is not production tested, but is supported by characterization data at initial product release.
2
See Typical Performance Characteristics.
3
Specifications before calibration. Channel system calibration reduces these errors to the order of the noise.
4
Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error.
5
Specifications before calibration. ADC zero-scale self-calibration or channel zero-scale system calibration reduce this error to the order of the noise.
6
For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage
range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register
value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for details.
7
For specified performance. If the analog input absolute voltage (referred to AGND) changes more than 0.5 V during one conversion time, the result could be affected
by distortion in the input buffer. This limit does not apply to analog input absolute voltages below 3 V.
8
If chopping is enabled or when switching between channels, a dynamic current charges the capacitance of the multiplexer. See the circuit description for details.
9
For specified performance. Part is functional with lower V
REF
.
10
Dynamic current charging the sigma-delta modulator input switching capacitor.
11
Outside the specified calibration range, calibration is possible but the performance may degrade.
12
These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.
13
With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register
).
14
External MCLKIN = 0 V or DV
DD
, digital inputs = 0 V or DV
DD
, P0 and P1 = 0 V or AV
DD
.
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