參數(shù)資料
型號: AD7739BRU-REEL
廠商: Analog Devices Inc
文件頁數(shù): 15/32頁
文件大?。?/td> 0K
描述: IC ADC 24BIT 8CH SIG-DEL 24TSSOP
標準包裝: 2,500
位數(shù): 24
采樣率(每秒): 15.1k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 100mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;8 個單端,雙極;4 個差分,單極;4 個差分,雙極
配用: EVAL-AD7739EBZ-ND - BOARD EVAL FOR AD7739
AD7739
Data Sheet
Rev. A | Page 22 of 32
RESET
The AD7739 can be reset by the RESET pin or by writing a reset
sequence to the AD7739 serial interface. The reset sequence is
N × 0 + 32 × 1, which can be the data sequence 0x00 + 0xFF +
0xFF + 0xFF + 0xFF in a byte-oriented interface.
The AD7739 also features a power-on reset with a trip point
of 2 V and goes to the defined default state after power-on.
It is the responsibility of the system designer to prevent an
unwanted write operation to the AD7739. The unwanted write
operation can happen when a spurious clock appears on the
SCLK while the CS pin is low. Note that if the AD7739 interface
signals are floating or undefined at system power-on, the part
can be inadvertently configured into an unknown state. This
can be easily overcome by initiating either a hardware reset
event or a 32 ones reset sequence as the first step in the system
configuration.
ACCESS THE AD7739 REGISTERS
All communications to the part start with a write operation to
the communications register followed by either reading or writing
the addressed register. In a simultaneous read-write interface
(such as SPI), write 0 to the AD7739 while reading data.
Figure 15 shows the AD7739 interface read sequence for the
ADC status register.
SINGLE CONVERSION AND READING DATA
When the mode register is being written, the ADC status byte
is cleared and the RDY pin goes high, regardless of its previous
state. When the single conversion command is written to the
mode register, the ADC starts the conversion on the channel
selected by the address of the mode register. After the conversion
is completed, the data register is updated, the mode register is
changed to idle mode, the relevant RDY bit is set, and the RDY
pin goes low. The RDY bit is reset and the RDY pin returns high
when the relevant channel data register is being read.
Figure 16 shows the digital interface signals executing a single
conversion on Channel 0, waiting for the RDY pin to go low,
and reading the Channel 0 data register.
DUMP MODE
When the dump bit in the mode register is set to 1, the channel
status register is read immediately by a read of the channel data
register, regardless of whether the status or the data register is
addressed through the communications register. The DIN pin
must not be high while reading 24-bit data in dump mode;
otherwise, the AD7739 is reset.
Figure 17 shows the digital interface signals executing a single
conversion on Channel 0, waiting for the RDY pin to go low,
and reading the Channel 0 status register and data register in
the dump mode.
Figure 16. Serial Interface Signals—Single Conversion Command and 16-Bit Data Reading
Figure 17. Serial Interface Signals—Single Conversion Command, 16-Bit Data Reading, Dump Mode
DIN
SCLK
CS
DOUT
WRITE
COMMUNICATIONS
REGISTER
WRITE
MODE
REGISTER
RDY
CONVERSION TIME
READ DATA REGISTER
0x38
0x40
0x48
(0x00)
DATA
WRITE
COMMUNICATIONS
REGISTER
03742-0-017
DIN
SCLK
CS
DOUT
WRITE
COMMUNICATIONS
REGISTER
WRITE
MODE
REGISTER
RDY
CONVERSION TIME
READ DATA
REGISTER
READ
CHANNEL
STATUS
0x38
0x48
WRITE
COMMUNICATIONS
REGISTER
(0x00)
STATUS
DATA
03742-0-018
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