參數(shù)資料
型號(hào)： AD7734BRU
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/32頁(yè)
文件大小： 0K
描述： IC ADC 24BIT 4-CH 28-TSSOP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 24
采樣率（每秒）： 15.4k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 100mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 4 個(gè)單端，單極；4 個(gè)單端，雙極
配用： EVAL-AD7734EBZ-ND - BOARD EVALUATION FOR AD7734
AD7734
Data Sheet
Rev. A | Page 26 of 32
CIRCUIT DESCRIPTION
The AD7734 is a sigma-delta ADC that is intended for the
measurement of wide dynamic range, low frequency signals in
industrial process control, instrumentation, and PLC systems.
It contains thin film resistor dividers, a multiplexer, an input
buffer, a sigma-delta (or charge balancing) ADC, a digital filter,
a clock oscillator, a digital I/O port, and a serial communi-
cations interface.
ANALOG FRONT END
The AD7734 features four single-ended analog inputs. The on-
chip thin film resistor dividers allow ±10 V, ±5 V, 0 V to +10 V,
and 0 V to +5 V input signals to be connected directly to the
analog input pins.
The resistor divider input stage is followed by the multiplexer
and then by a wide bandwidth, fast settling time differential
input buffer capable of driving the dynamic load of a high speed
sigma-delta modulator.
In normal circuit configuration, the BIAS0 to BIAS3 and
BIASHI pins are connected to the 2.5 V (reference) voltage
source and the BIASLO pin is connected to 0 V. This ensures
that the differential signal seen by the internal input buffer is
within its absolute/common-mode range of AGND + 200 mV
to AVDD – 300 mV.
The AD7734 AIN voltage should be within the specified
nominal (up to ±10 V) input range, otherwise the performance
on channel might degrade (see the Analog Input’s Extended
If the BIAS pins are in normal configuration, the AIN pin
absolute voltage up to ±16.5 V does not degrade the adjacent
channel’s performance. An AIN absolute voltage over ±16.5 V
results in current flowing through the internal protection
diodes located behind the thin film resistors and the adjacent
channel can be affected.
The AIN pins are “overvoltage tolerant.” However, the absolute
maximum AIN voltage of ±50 V must never be exceeded.
Note that the OVR bit in the channel status register is generated
digitally from the conversion result and indicates the sigma-
delta modulator (nominal) overrange. The OVR bit DOES NOT
indicate exceeding the AIN pin absolute voltage limits.
Figure 23 shows the AD7734 analog input internal structure.
BIAS
AIN
1R
7R
108.5k
15.5k
AVDD
MUX
PROTECTION
DIODES
AGND
2.1875V ± 1.25V
2.5V
±10V
BUFFER
Figure 23. Simplified Analog Input Internal Structure
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