參數(shù)資料
型號(hào)： AD7721SQ
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC
中文描述： 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL/PARALLEL ACCESS, CDIP28
封裝： CERDIP-28
文件頁(yè)數(shù)： 3/16頁(yè)
文件大?。?/td> 259K
代理商： AD7721SQ
SPECIFICATIONS
1
Parameter
PARALLE L MODE ONLY
ST AT IC PERFORMANCE
Resolution
Minimum Resolution for Which
No Missing Codes Is Guaranteed
Differential Nonlinearity
Integral Nonlinearity
DC CMRR
Offset Error
2
Unipolar Mode
Bipolar Mode
Full-Scale Error
2, 3
Unipolar Mode
Bipolar Mode
Unipolar Offset Drift
Bipolar Offset Drift
ANALOG INPUT S
Signal Input Span (VIN1–VIN2):
Bipolar Mode
Unipolar Mode
Maximum Input Voltage
Minimum Input Voltage
Input Sampling Capacitance
Input Sampling Rate
Differential Input Impedance
REFERENCE INPUT S
V
REFIN
REFIN Input Current
DYNAMIC SPECIFICAT IONS
Signal to (Noise + Distortion)
T otal Harmonic Distortion
Frequency Response
0 kHz–140 kHz
152.8 kHz
172.67 kHz to 9.827 MHz
CLOCK
CLK Duty Ratio
V
CLK H
, CLK High Voltage
V
CLK L
, CLK Low Voltage
LOGIC INPUT S
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
, Input Current
C
IN
, Input Capacitance
LOGIC OUT PUT S
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
DV
DD
I
DD
(T otal from AV
DD
, DV
DD
)
Power Consumption
Power Consumption
A Version
S Version
Units
T est Conditions/Comments
12
12
12
12
Bits
Bits min
Guaranteed 12 Bits Monotonic
±
1/2
±
1/2
70
±
1/2
±
1/2
70
LSB typ
LSB typ
dB min
12-Bit Operation
Bipolar Mode
±
3.66
±
3.66
±
3.66
±
3.66
mV max
mV max
T ypically 0.61 mV
T ypically 0.61 mV
±
4.88
±
4.88
0.04
0.035
±
4.88
±
4.88
0.04
0.035
mV max
mV max
mV/
°
C typ
mV/
°
C typ
T ypically 0.61 mV
T ypically 1.22 mV
±
V
/2
0 to V
REFIN
AV
DD
0
1.6
2 f
CLK
31.25
±
V
/2
0 to V
REFIN
AV
DD
0
1.6
2 f
CLK
31.25
Volts max
Volts max
Volts
Volts
pF typ
MHz
k
typ
UNI
= V
IH
UNI
= V
IL
Guaranteed by Design
With 10 MHz on CLK Pin
2.4 to 2.6
200
2.4 to 2.6
200
V min/V max
μ
A typ
70
–78
70
–78
dB min
dB max
Input Bandwidth 0 kHz to 140 kHz
Input Bandwidth 0 kHz to 152.8 kHz
±
0.05
–3
–72
±
0.05
–3
–72
dB max
dB min
dB min
45 to 55
0.7
×
DV
DD
0.3
×
DV
DD
45 to 55
0.7
×
DV
DD
0.3
×
DV
DD
% max
V min
V max
For Specified Operation
CLK Uses CMOS Logic
2.0
0.8
10
10
2.0
0.8
10
10
V min
V max
μ
A max
pF max
4.0
0.4
4.0
0.4
V min
V max
|I
OUT
|
≤
200
μ
A
|I
OUT
|
≤
1.6 mA
4.75/5.25
4.75/5.25
28.5
150
100
4.75/5.25
4.75/5.25
28.5
150
100
V min/V max
V min/V max
mA max
mW max
μ
W max
Digital Inputs Equal to 0 V or DV
DD
Active Mode
Standby Mode
NOT ES
1
Operating temperature range is as follows: A Version: –40
°
C to +85
°
C; S Version: –55
°
C to +125
°
C.
2
Applies after calibration at temperature of interest.
3
Full-scale error applies to both positive and negative full-scale error. T he ADC gain is calibrated w.r.t. the voltage on the REFIN pin.
Specifications subject to change without notice.
–3–
REV. A
(AV
DD
= +5 V
6
5%; DV
DD
= +5 V
6
5%; AGND = DGND = 0 V, f
CLK
= 10 MHz,
REFIN= +2.5 V; T
A
= T
MN
to T
MAX
, unless otherwse noted)
AD7721
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