參數(shù)資料
型號: AD7720
廠商: Analog Devices, Inc.
英文描述: CMOS Sigma-Delta Modulator
中文描述: 的CMOSΣ-Δ調(diào)制器
文件頁數(shù): 12/16頁
文件大小: 232K
代理商: AD7720
AD7720
–12–
REV. 0
12pF
1k
V
1k
V
1k
V
12pF
1k
V
220nF
374k
V
1nF
VIN(–)
1/2
OP275
VIN(+)
REF1
REF2
100nF
DIFFERENTIAL
INPUT = 2.5V p-p
VIN(–) BIAS
VOLTAGE = 1.25V
AIN =
6
1.25V
1/2
OP275
1k
V
374k
V
10nF
1nF
Figure 28. Single-Ended Analog Input for Bipolar Mode
Operation
12pF
1k
V
AIN =
6
0.625V
1k
V
1k
V
12pF
1k
V
1/2
OP275
220nF
R
R
1nF
VIN(–)
1nF
1/2
OP275
VIN(+)
DIFFERENTIAL
INPUT = 2.5V p-p
COMMON MODE
VOLTAGE = 2.5V
REF1
OP07
REF2
100nF
Figure 29. Single-Ended to Differential Analog Input
Circuit for Bipolar Mode Operation
T he 1 nF capacitors at each ADC input store charge to aid the
amplifier settling as the input is continuously switched. A resis-
tor in series with the drive amplifier output and the 1 nF input
capacitor may also be used to create an antialias filter.
Clock Generation
T he AD7720 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the
ADC. T he connection diagram for use with the crystal is shown
in Figure 30. Consult the crystal manufacturer’s recommenda-
tion for the load capacitors.
1M
V
XTAL
MCLK
Figure 30. Crystal Oscillator Connection
An external clock must be free of ringing and have a minimum
rise time of 5 ns. Degradation in performance can result as high
edge rates increase coupling that can generate noise in the sam-
pling process. T he connection diagram for an external clock
source (Figure 31) shows a series damping resistor connected
between the clock output and the clock input to the AD7720.
T he optimum resistor will depend on the board layout and the
impedance of the trace connecting to the clock input.
CLOCK
CIRCUITRY
MCLK
25–150
V
Figure 31. External Clock Oscillator Connection
A low phase noise clock should be used to generate the ADC
sampling clock because sampling clock jitter effectively modu-
lates the input signal and raises the noise floor. T he sampling
clock generator should be isolated from noisy digital circuits,
grounded and heavily decoupled to the analog ground plane.
T he sampling clock generator should be referenced to the ana-
log ground plane in a split ground system. However, this is not
always possible because of system constraints. In many cases,
the sampling clock must be derived from a higher frequency
multipurpose system clock that is generated on the digital
ground plane. If the clock signal is passed between its origin on
a digital plane to the AD7720 on the analog ground plane, the
ground noise between the two planes adds directly to the clock
and will produce excess jitter. T he jitter can cause unwanted
degradation in the signal-to-noise ratio and also produce un-
wanted harmonics.
T his can be somewhat remedied by transmitting the sampling
clock signal as a differential one, using either a small RF trans-
former or a high speed differential driver and receiver such as
PECL. In either case, the original master system clock should
be generated from a low phase noise crystal oscillator.
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