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參數(shù)資料
| 型號(hào)： | AD7719BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MS-153AE, TSSOP-28 |
| 文件頁數(shù)： | 26/40頁 |
| 文件大小： | 367K |
| 代理商： | AD7719BRU |
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REV. 0
AD7719
–26–
Main ADC Data Result Registers (DATA0): (A3, A2, A1, A0 = 0, 1, 0, 1; Power-On Reset = 000000 Hex)
The conversion results for the Main ADC channel is stored in the Main ADC data register (DATA0). This register is either 16 or
24 bits wide, depending on the status of the WL bit in the Main ADC control register (AD0CON). This is a read only register. On
completion of a read from this register the RDY0 bit in the status register is cleared.
Aux ADC Data Result Registers (DATA1): (A3, A2, A1, A0 = 0, 1, 1, 0; Power-On Reset = 0000 Hex)
The conversion results for the Aux ADC channel is stored in the aux ADC data register (DATA1). This register is 16 bits wide and
is a read only register. On completion of a read from this register the RDY1 bit in the status register is cleared.
Main ADC Offset Calibration Coefficient Registers (OF0): (A3, A2, A1, A0 = 1, 0, 0, 0; Power-On Reset = 800000 Hex)
The offset calibration registers hold the 24-bit data offset calibration coefficient for the Main ADC. There are three registers associated
with the Main ADC channel. In fully-differential operating mode there are two input channels and a register is dedicated to each
input. When operating in pseudo-differential mode the Main ADC can be configured for 3 input channels and there is a dedicated
register for each pseudo-differential input. These registers have a power-on reset value of 800000H. The channel bits in association
with the communication register address for the OF0 register allow access to these registers. These registers are read/write registers.
The calibration registers can only be written to if the ADC is inactive (MD bits in the mode register = 000 or 001 or both AD0EN
and AD1EN bits in the control registers are cleared). Reading of the calibration registers does not clear the RDY0 bit.
Aux ADC Offset Calibration Coefficient Registers (OF1): (A3, A2, A1, A0 = 1, 0, 0, 1; Power-On Reset = 8000 Hex)
The offset calibration register OF1 holds the 16-bit data offset calibration coefficient for the Aux ADC. This register has a power-
on-reset value of 8000 Hex. The channel bits in association with the communication register address for the OF1 register allow
access to these registers. These registers are read/write registers. The calibration registers can only be written to if the ADC is
inactive (MD bits in the mode register = 000 or 001 or both AD0EN and AD1EN bits in the control registers are cleared). Reading
of the calibration registers does not clear the RDY1 bit.
Main ADC Gain Calibration Coefficient Registers (GNO): (A3, A2, A1, A0 = 1, 0, 1, 0; Power-On Reset = 5XXXX5 Hex)
The gain calibration registers hold the 24-bit data gain calibration coefficient for the Main ADC. These registers are configured at
power-on with factory calculated internal full-scale calibration coefficients. Every device will have different coefficients. However,
these bytes will be automatically overwritten if an internal or system full-scale calibration is initiated by the user via MD2
–
0 bits in
the Mode register. There are three gain calibration registers associated with the Main ADC channel. In fully-differential operating
mode there are two input channels and a register is dedicated to each input. When operating in pseudo-differential mode the Main
ADC can be configured for three input channels and there is a dedicated register for each pseudo-differential input. These registers
are read/write registers. The calibration registers can only be written to if the ADC is inactive (MD bits in the mode register =000 or
001 or both AD0EN and AD1EN bits in the control registers are cleared). Reading of the calibration registers does not clear the
RDY1 bit.
Aux ADC Gain Calibration Coefficient Registers (GN1): (A3, A2, A1, A0 = 1, 0, 1, 1; Power-On Reset = 59XX Hex)
The gain calibration register GN1 holds the 16-bit data gain calibration coefficient for the Aux ADC. This register is configured at
power-on with factory calculated internal zero-scale calibration coefficients. Every device will have different coefficients. However,
these coefficients will be automatically overwritten if an internal or system zero-scale calibration is initiated by the user via the
MD2
–
0 bits in the MODE register. These registers are read/write registers. The calibration registers can only be written to if the
ADC is inactive (MD bits in the mode register = 000 or 001 or both AD0EN and AD1EN bits in the control registers are cleared).
Reading of the calibration registers does not clear the RDY1 bit.
ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1; Power-On Reset = 0X Hex)
This register is a read-only 8-bit register. The contents are used to determine the die revision of the AD7719. Table XVII indicates
the bit locations.
Table XVII. ID Register Bit Designations
7
D
I
6
D
I
5
D
I
4
D
I
3
D
I
2
D
I
1
D
I
0
D
I
0
0
0
0
X
X
X
X
User Nonprogrammable Test Registers
The AD7719 contains two test registers. The bits in this test register control the test modes of the AD7719 which are used for the
testing of the device.
The user is advised not to change the contents of these registers
.
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