參數(shù)資料
型號(hào)： AD7718BR-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 20/44頁
文件大小： 0K
描述： IC ADC 24BIT R-R 8/10CH 28-SOIC
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 24
采樣率（每秒）： 1.37k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 3.84mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 5 個(gè)差分，單極；5 個(gè)差分，雙極；10 偽差分，單極；10 偽差分，雙極
配用： EVAL-AD7718EBZ-ND - BOARD EVALUATION FOR AD7718
REV. 0
AD7708/AD7718
–27–
Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On-Reset = 00Hex)
The Mode Register is an 8-bit register from which data can be read or to which data can be written. This register configures the
operating modes of the AD7708/AD7718. Table XV outlines the bit designations for the Mode Register. MR7 through MR0 indi-
cate the bit location, MR denoting the bits are in the Mode Register. MR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit.
7
R
M6
R
M5
R
M4
R
M3
R
M2
R
M1
R
M0
R
M
P
O
H
C
)
0
(
)
0
(
F
U
B
G
E
N)
0
(
L
E
S
F
E
R)
0
(
N
O
C
H
C)
0
(
D
P
C
S
O)
0
(
2
D
M)
0
(
1
D
M)
0
(
0
D
M
Table XV. Mode Register Bit Designations
Bit
Location
Mnemonic
Description
MR7
CHOP
If this bit is cleared, chopping is enabled. When this bit is set chopping is disabled. The default is for
chop enabled.
MR6
NEGBUF
This bit controls the operation of the input buffer on the AINCOM input when a channel is config-
ured for pseudo-differential mode of operation. If cleared, the analog negative input (AINCOM) is
unbuffered allowing it to be tied to AGND in single-ended input configuration. If this bit is set the
analog negative input (AINCOM) is buffered, placing a restriction on its common-mode input range.
MR5
REFSEL
If this bit is cleared, the reference selected is REFIN1(+) and REFIN1(–) for the active channel. If
this bit is set, the reference selected is REFIN2(+) and REFIN2(–) for the active channel. The con-
tents of the CHCON bit overrides the REFSEL bit. If the ADC is configured in five fully-differential
or 10 pseudo-differential input channel mode, the REFSEL bit setting is irrelevant as only one
reference input is available. VREF Select implemented using the REFSEL bit enables the user to
perform both absolute and ratiometric measurements.
MR4
CHCON
When cleared the device is configured as an 8-input channel converter, configured as eight pseudo-
differential input channels with respect to AINCOM or four differential input arrangements
with two reference input selection options. When set the device is configured as a 10 pseudo-
differential input or a five differential input channel arrangement with a single reference
input option.
MR3
OSCPD
Oscillator Power-Down Bit.
If this bit is set, placing the AD7708/AD7718 in standby mode will stop the crystal oscillator reducing
the power drawn by these parts to a minimum. The oscillator will require 300 ms to begin oscillating
when the ADC is taken out of standby mode. If this bit is cleared, the oscillator is not shut off when
the ADC is put into standby mode and will not require the 300 ms start-up time when the ADC is
taken out of standby.
MR2–MR0
MD2–MD0
ADC Mode Bits.
These bits select the operational mode of the ADC as follows:
MD2
MD1
MD0
0
Power-Down Mode (Power-On Default)
0
1
Idle Mode
In Idle Mode the ADC filter and modulator are held in a reset state although the modulator clocks
are still provided.
0
1
0
Single Conversion Mode
In Single Conversion Mode, a single conversion is performed on the enabled channels. On comple-
tion of the conversion the ADC data registers are updated, the relevant flags in the STATUS register
are written, and idle mode is reentered with the MD2–MD0 being written accordingly to 001.
0
1
Continuous Conversion
In continuous conversion mode, the ADC data registers are regularly updated at the selected update
rate (see Filter register).
1
0
Internal Zero-Scale Calibration
Internal short automatically connected to the enabled channel(s)
1
0
1
Internal Full-Scale Calibration
External VREF is connected automatically to the ADC input for this calibration.
1
0
System Zero-Scale Calibration
User should connect system zero-scale input to the channel input pins as selected by CH3–CH0 bits
in the control registers.
1
System Full-Scale Calibration
User should connect system full-scale input to the channel input pins as selected by CH3–CH0 bits
in the control registers.
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