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參數(shù)資料
| 型號： | AD7716BS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 22-Bit Data Acquisition System |
| 中文描述： | 4-CH 22-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 430K |
| 代理商： | AD7716BS |
REV. A
–7–
AD7716
PIN DESCRIPTION
Pin
Description
AV
DD
Analog Positive Supply, +5 V Nominal. This supplies +ve power to the analog modulators. AV
DD
& DV
DD
must be tied together externally.
Digital Positive Supply, +5 V Nominal. This supplies +ve power to the digital filter and input/output registers.
Analog Negative Supply, –5 V nominal. This supplies –ve power to the analog modulators.
A high pulse on this input pin synchronizes the sampling point on the four input channels. It can be used in a
multichannel system to ensure simultaneous sampling. This also resets the digital interface to a known state.
The three address input pins, A0, A1 and A2 give the device a unique address. This information is contained in
the output data stream from the device.
Clock Input for External Clock.
Clock Output which is used to generate an internal master clock by connecting a crystal between CLKOUT and
CLKIN. If an external clock is used then CLKOUT is not connected.
This digital input determines the device interface mode. If it is hardwired low, then the Master Mode interface is
enabled whereas if it is high, the Slave Mode interface is enabled.
This is an active-high, level-triggered digital input which is used to enable the output data stream. This input
may be used to cascade several devices in a multichannel system.
Digital output which goes high at the end of a complete 4-channel data transfer. This can be connected to the
CASCIN of the next device in a multichannel system to ensure proper control of the data transfer.
Receive Frame Synchronization signal for theserial output data stream. This can be an input or output depending
on the interface mode.
Serial Data Input/Output Pin.
Serial Clock Input/Output. The SCLK pin is configured as an input or output, depending on the state of the
Mode pin.
Data Ready Output. A falling edge indicates that a new word is available for transmission. It will return high
when 4, 32-bit words have been transmitted. It also goes high for one clock cycle, when a new word is being
loaded into the output register. Data should not be read during this period.
Transmit Frame Sync input for programming the on-chip Control Register.
Digital Data Input. This is contained in the digital data stream sent from the device.
Digital Outputs. These two digital outputs can be programmed from the on-chip Control Register. They can
be used to control calibration signals at the front end.
Reference Input, Nominally 2.5 V.
Analog Ground. Ground reference for analog circuitry.
Digital Ground. Ground return for digital circuitry.
Analog Input Pins. The analog input range is
±
2.5 V.
DV
DD
AV
SS
RESET
A0–A2
CLKIN
CLKOUT
MODE
CASCIN
CASCOUT
RFS
SDATA
SCLK
DRDY
TFS
D
IN
1
D
OUT
1, D
OUT
2
V
REF
AGND
DGND
A
IN
1–A
IN
4
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