Parameter1 Min Typ Max Unit Conditions/Comments LOGIC OUTPUTS (Including M" />
參數(shù)資料
型號： AD7715ARUZ-3REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 34/40頁
文件大小： 0K
描述： IC ADC 16BIT SIGMA-DELTA 16TSSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 9.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個差分，單極；1 個差分，雙極
配用： EVAL-AD7715-3EBZ-ND - BOARD EVALUATION FOR AD7715
AD7715
Rev. D | Page 4 of 40
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
LOGIC OUTPUTS (Including MCLK OUT)
VOL, Output Low Voltage
0.4
V
ISINK = 800 μA except for MCLK OUT12; DVDD = 5 V
VOL, Output Low Voltage
0.4
V
ISINK = 100 μA except for MCLK OUT12; DVDD = 3.3 V
VOH, Output High Voltage
4.0
V
ISOURCE = 200 μA except for MCLK OUT12; DVDD = 5 V
VOH, Output High Voltage
DVDD 0.6
V
ISOURCE = 100 μA except for MCLK OUT12; DVDD = 3.3 V
Floating State Leakage Current
±10
μA
Floating State Output Capacitance13
9
pF
Data Output Coding
Binary
Unipolar mode
Offset binary
Bipolar mode
1 Temperature range as follows: A version, 40°C to +85°C.
2 A calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the
temperature of interest.
3 Recalibration at any temperature removes these drift errors.
4 Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.
5 Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.
6 Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and full-scale error–bipolar zero error for
bipolar ranges.
7 Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.
8 These numbers are guaranteed by design and/or characterization.
9 This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN() does not go more positive than AVDD + 30 mV or go more negative
than AGND 30 mV.
10 The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(). The absolute voltage on the analog inputs should not go more positive
than AVDD + 30 mV or go more negative than AGND 30 mV.
11 VREF = REF IN(+) REF IN().
12 These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
13 Sample tested at 25°C to ensure compliance.
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