參數(shù)資料
型號： AD7714YR
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC
中文描述： 5-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封裝： WSOIC-24
文件頁數(shù)： 5/40頁
文件大小： 306K
代理商： AD7714YR
Parameter
STATIC PERFORMANCE
No Missing Codes
Y Versions
1
Units
Conditions/Comments
24
22
18
15
12
See Tables I to IV
±
0.001
See Note 2
0.4
0.1
See Note 2
0.4
0.1
See Note 2
0.4
0.1
See Note 2
0.2
Bits min
Bits min
Bits min
Bits min
Bits min
Guaranteed by Design. For Filter Notches
≤
60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
Depends on Filter Cutoffs and Selected Gain
Filter Notches
≤
60 Hz.
Output Noise
Integral Nonlinearity
Unipolar Offset Error
Unipolar Offset Drift
3
% of FSR max
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Bipolar Zero Error
Bipolar Zero Drift
3
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Positive Full-Scale Error
4
Full-Scale Drift
3, 5
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2, 4
For Gains of 8, 16, 32, 64, 128
Gain Error
6
Gain Drift
3, 7
ppm of FSR/
°
C typ
% of FSR max
% of FSR max
μ
V/
°
C typ
μ
V/
°
C typ
Bipolar Negative Full-Scale Error
2
±
0.0015
±
0.003
1
0.6
AV
DD
= 5 V. Typically
±
0.0004%
AV
= 3 V. Typically
±
0.0004%
For Gains of 1 to 4
For Gains of 8 to 128
Specifications for AIN and REF IN Unless Noted
At DC. Typically 102 dB.
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
f
NOTCH
Bipolar Negative Full-Scale Drift
3
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR)
8
Normal-Mode 50 Hz Rejection
8
Normal-Mode 60 Hz Rejection
8
Common-Mode 50 Hz Rejection
8
Common-Mode 60 Hz Rejection
8
Absolute/Common-Mode REF IN Voltage
8
Absolute/Common-Mode AIN Voltage
8,
9
90
100
100
150
150
AGND to AV
AGND – 30 mV
AV
+ 30 mV
AGND + 50 mV
AV
DD
– 1.5 V
1
7
0 to +V
/GAIN
11
V
/GAIN
GAIN
×
f
CLKIN
/64
f
CLKIN
/8
dB min
dB min
dB min
dB min
dB min
V min to V max
V min
V max
V min
V max
nA max
pF max
nom
nom
BUF Bit of Setup Register = 0
Absolute/Common-Mode AIN Voltage
8, 9
BUF Bit of Setup Register = 1
AIN DC Input Current
8
AIN Sampling Capacitance
8
AIN Differential Voltage Range
10
Unipolar Input Range (B/U Bit of Filter High Register = 1)
Bipolar Input Range (B/U Bit of Filter High Register = 0)
For Gains of 1 to 4
For Gains of 8 to 128
AIN Input Sampling Rate, f
S
Reference Input Range
REF IN(+) – REF IN(–) Voltage
REF IN(+) – REF IN(–) Voltage
REF IN Input Sampling Rate, f
S
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
V
INL
, Input Low Voltage
1/1.75
1/3.5
f
CLK IN
/64
V min/max
V min/max
AV
DD
= 2.7 V to 3.3 V. V
= 1.25
±
1% for Specified Performance
AV
DD
= 4.75 V to 5.25 V. V
REF
= 2.5
±
1% for Specified Performance
±
10
μ
A max
0.8
0.4
2.4
2
V max
V max
V min
V min
DV
DD
= 5 V
DV
DD
= 3 V
DV
DD
= 5 V
DV
DD
= 3 V
DV
DD
= 5 V NOMINAL
V
INH
, Input High Voltage
SCLK & DIN Only (Schmitt Triggered Input)
V
T+
V
T–
V
– V
SCLK & DIN Only (Schmitt Triggered Input)
V
T+
V
T–
V
– V
MCLK In Only
V
INL
, Input Low Voltage
V
, Input High Voltage
MCLK In Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
1.4/3
0.8/1.4
0.4/0.8
V min/V max
V min/V max
V min/V max
DV
DD
= 3 V NOMINAL
1/2.5
0.4/1.1
0.375/0.8
V min/V max
V min/V max
V min/V max
DV
DD
= 5 V NOMINAL
0.8
3.5
V max
V min
DV
DD
= 3 V NOMINAL
0.4
2.5
V max
V min
0.4
0.4
4
V max
V max
V min
I
SINK
= 800
μ
A with DV
DD
= 5 V. Except for MCLK OUT
12
I
SINK
= 100
μ
A with DV
DD
= 3 V. Except for MCLK OUT
12
I
SOURCE
= 200
μ
A with DV
DD
= 5 V. Except for MCLK OUT
12
AD7714Y–SPECIFICATIONS
(AV
DD
= DV
DD
= +2.7V to +3.3V or 4.75 V to 5.25 V, REF IN(+) = +1.25V; with AV
DD
= 3 V
and +2.5 V with AV
DD
= 5 V; REFIN(–) = AGND; MCLK IN = 2.4576MHz unless otherwise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.)
AD7714
REV. C
–5–
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