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參數(shù)資料
| 型號(hào)： | AD7713AQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Loop-Powered Signal Conditioning ADC |
| 中文描述： | 3-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁(yè)數(shù)： | 17/28頁(yè) |
| 文件大?。?/td> | 516K |
| 代理商： | AD7713AQ |
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2
–17–
REV. C
AD7713
The AD7713 also provides the facility to write to the on-chip
calibration registers, and in this manner the span and offset for
the part can be adjusted by the user. The offset calibration regis-
ter contains a value which is subtracted from all conversion
results, while the full-scale calibration register contains a value
which is multiplied by all conversion results. The offset calibra-
tion coefficient is subtracted from the result prior to the multi-
plication by the full-scale coefficient. In the first three modes
outlined here, the
DRDY
line indicates that calibration is com-
plete by going low. If
DRDY
is low before (or goes low during)
the calibration command, it may take up to one modulator cycle
before
DRDY
goes high to indicate that calibration is in
progress. Therefore, the
DRDY
line should be ignored for up
to one modulator cycle after the last bit of the calibration com-
mand is written to the control register.
Self-Calibration
In the self-calibration mode with a unipolar input range, the
zero-scale point used in determining the calibration coefficients
is with both inputs shorted (i.e., AIN1(+) = AIN1(–) =
V
BIAS
for AIN1 and AIN2 and AIN3 = V
BIAS
for AIN3 ) and the
full-scale point is V
REF
. The zero-scale coefficient is determined
by converting an internal shorted inputs node. The full-scale co-
efficient is determined from the span between this shorted in-
puts conversion and a conversion on an internal V
REF
node. The
self-calibration mode is invoked by writing the appropriate val-
ues (0, 0, 1) to the MD2, MD1 and MD0 bits of the control
register. In this calibration mode, the shorted inputs node is
switched in to the modulator first and a conversion is performed;
the V
REF
node is then switched in, and another conversion is per-
formed. When the calibration sequence is complete, the calibration
coefficients updated and the filter resettled to the analog input
voltage, the
DRDY
output goes low. The self-calibration proce-
dure takes into account the selected gain on the PGA.
For bipolar input ranges in the self-calibrating mode, the
sequence is very similar to that just outlined. In this case, the
two points that the AD7713 calibrates are midscale (bipolar
zero) and positive full scale.
System Calibration
System calibration allows the AD7713 to compensate for system
gain and offset errors as well as its own internal errors. System
calibration performs the same slope factor calculations as self-
calibration but uses voltage values presented by the system to
the AIN inputs for the zero and full-scale points. System cali-
bration is a two-step process. The zero-scale point must be pre-
sented to the converter first. It must be applied to the converter
before the calibration step is initiated and remain stable until the
step is complete. System calibration is initiated by writing the
appropriate values (0, 1, 0) to the MD2, MD1 and MD0 bits of
the control register. The
DRDY
output from the device will sig-
nal when the step is complete by going low. After the zero-scale
point is calibrated, the full-scale point is applied and the second
step of the calibration process is initiated by again writing the
appropriate values (0, 1, 1) to MD2, MD1 and MD0. Again the
full-scale voltage must be set up before the calibration is initi-
ated, and it must remain stable throughout the calibration step.
DRDY
goes low at the end of this second step to indicate that
the system calibration is complete. In the unipolar mode, the
system calibration is performed between the two endpoints of
the transfer function; in the bipolar mode, it is performed be-
tween midscale and positive full scale.
This two-step system calibration mode offers another feature.
After the sequence has been completed, additional offset or gain
calibrations can be performed by themselves to adjust the zero
reference point or the system gain. This is achieved by perform-
ing the first step of the system calibration sequence (by writing
0, 1, 0 to MD2, MD1, MD0). This will adjust the zero-scale or
offset point but will not change the slope factor from what was
set during a full system calibration sequence.
System calibration can also be used to remove any errors from
an antialiasing filter on the analog input. A simple R, C anti-
aliasing filter on the front end may introduce a gain error on the
analog input voltage but the system calibration can be used to
remove this error.
System Offset Calibration
System offset calibration is a variation of both the system cali-
bration and self-calibration. In this case, the zero-scale point
for the system is presented to the AIN input of the converter.
System offset calibration is initiated by writing 1, 0, 0 to MD2,
MD1, MD0. The system zero-scale coefficient is determined by
converting the voltage applied to the AIN input, while the full-
scale coefficient is determined from the span between this AIN
conversion and a conversion on V
REF
. The zero-scale point
should be applied to the AIN input for the duration of the cali-
bration sequence. This is a one-step calibration sequence with
DRDY
going low when the sequence is completed. In the uni-
polar mode, the system offset calibration is performed between
the two endpoints of the transfer function; in the bipolar mode,
it is performed between midscale and positive full scale.
Background Calibration
The AD7713 also offers a background calibration mode where
the part interleaves its calibration procedure with its normal
conversion sequence. In the background calibration mode, the
same voltages are used as the calibration points as are used in
the self-calibration mode, i.e., shorted inputs and V
REF
. The
background calibration mode is invoked by writing 1, 0, 1 to
MD2, MD1, MD0 of the control register. When invoked, the
background calibration mode reduces the output data rate of the
AD7713 by a factor of six while the –3 dB bandwidth remains
unchanged. Its advantage is that the part is continually perform-
ing calibration and automatically updating its calibration coeffi-
cients. As a result, the effects of temperature drift, supply sensitivity
and time drift on zero- and full-scale errors are automatically
removed. When the background calibration mode is turned on,
the part will remain in this mode until bits MD2, MD1 and
MD0 of the control register are changed. With background cali-
bration mode on, the first result from the AD7713 will be incor-
rect as the full-scale calibration will not have been performed.
For a step change on the input, the second output update will
have settled to 100% of the final value.
Table IV summarizes the calibration modes and the calibration
points associated with them. It also gives the duration from
when the calibration is invoked to when valid data is available to
the user.
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