參數(shù)資料
型號： AD7713AN
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： LC2MOS Loop-Powered Signal Conditioning ADC
中文描述： 3-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24
封裝： 0.300 INCH, PLASTIC, DIP-24
文件頁數(shù)： 2/28頁
文件大?。?/td> 516K
代理商： AD7713AN
Parameter
STATIC PERFORMANCE
No Missing Codes
A, S Versions
1
Units
Conditions/Comments
24
22
18
15
12
See Tables I & II
±
0.0015
See Note 4
1
0.3
See Note 4
0.5
0.25
See Note 4
0.5
0.25
2
±
0.004
1
0.3
Bits min
Bits min
Bits min
Bits min
Bits min
Guaranteed by Design. For Filter Notches
≤
12 Hz
For Filter Notch = 20 Hz
For Filter Notch = 50 Hz
For Filter Notch = 100 Hz
For Filter Notch = 200 Hz
Depends on Filter Cutoffs and Selected Gain
Filter Notches
≤
12 Hz; Typically
±
0.0003%
Output Noise
Integral Nonlinearity
Positive Full-Scale Error
2, 3
Full-Scale Drift
5
% of FSR max
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Unipolar Offset Error
2
Unipolar Offset Drift
5
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Bipolar Zero Error
2
Bipolar Zero Drift
5
μ
V/
°
C typ
μ
V/
°
C typ
ppm/
°
C typ
% of FSR max
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Gain Drift
Bipolar Negative Full-Scale Error
2
Bipolar Negative Full-Scale Drift
5
Typically
±
0.0006%
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
ANALOG INPUTS
Input Sampling Rate, f
Normal-Mode 50 Hz Rejection
6
Normal-Mode 60 Hz Rejection
6
AIN1, AIN2
7
Input Voltage Range
8
See Table III
100
100
dB min
dB min
For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
f
NOTCH
For Normal Operation. Depends on Gain Selected.
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
At DC
For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz,
±
0.02
×
f
NOTCH
0 to +V
REF9
±
V
REF
100
150
150
AGND to AV
DD
10
1
20
V max
V max
dB min
dB min
dB min
V min to V max
pA max
nA max
pF max
Common-Mode Rejection (CMR)
Common-Mode 50 Hz Rejection
6
Common-Mode 60 Hz Rejection
6
Common-Mode Voltage Range
10
DC Input Leakage Current @ +25
°
C
T
to T
Sampling Capacitance
6
AIN3
Input Voltage Range
Gain Error
Gain Drift
Offset Error
11
Input Impedance
NOTES
1
Temperature range is as follows: A Version, –40
°
C to +85
°
C; S Version, –55
°
C to +125
°
C.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20
μ
V typical after self-calibration
or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
These numbers are guaranteed by design and/or characterization.
7
The AIN1 and AIN2 analog inputs presents a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum
recommended source resistance depends on the selected gain.
8
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2 (–) inputs. The input
voltage range on the AIN3 input is with respect to AGND. The absolute voltage on the AIN1 and AIN2 inputs should not go more positive than A V
DD
+ 30 mV or
more negative than AGND – 30 mV.
9
V
REF
= REF IN(+) – REF IN(–).
10
This common-mode voltage range is allowed provided that the input voltage on AIN(+) and AIN(–) does not exceed AV
DD
+ 30 mV and AGND – 30 mV.
11
This error can be removed using the system calibration capabilities of the AD7713. This error is not removed by the AD7713’s self-calibration feature. The offset
drift on the AIN3 input is four times the value given in the Static Performance section.
0 to + 4
×
V
REF
±
0.05
1
4
30
V max
% typ
ppm/
°
C typ
mV max
k
min
For Normal Operation. Depends on Gain Selected
Additional Error Contributed by Resistor Attenuator
Additional Drift Contributed by Resistor Attenuator
Additional Error Contributed by Resistor Attenuator
–2–
REV. C
(AV
DD
= +5 V
6
5%; DV
DD
= +5 V
6
5%; REF IN(+) = +2.5 V; REF IN(–) = AGND;
MCLK IN = 2 MHz unless otherwise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.)
AD7713–SPECIFICATIONS
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