參數(shù)資料
型號(hào)： AD7712*
廠商： Analog Devices, Inc.
英文描述： Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C
中文描述： LC2MOS信號(hào)調(diào)理模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù)： 8/28頁(yè)
文件大?。?/td> 229K
REV. E
–8–
AD7712
Pin
Mnemonic
Function
21
DRDY
Logic output. A falling edge indicates that a new output word is available for transmission. The
DRDY
pin
will return high upon completion of transmission of a full output word.
DRDY
is also used to indicate
when the AD7712 has completed its on-chip calibration sequence.
Serial Data. Input/Output with serial data being written to either the control register or the calibration
registers and serial data being accessed from the control register, calibration registers or the data register.
During an output data read operation, serial data becomes active after
RFS
goes low (provided
DRDY
is
low). During a write operation, valid serial data is expected on the rising edges of SCLK when
TFS
is low.
The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.
Digital Supply Voltage, +5 V. DV
DD
should not exceed AV
DD
by more than 0.3 V in normal operation.
Ground reference point for digital circuitry.
22
SDATA
23
24
DV
DD
DGND
TERMINOLOGY
INTEGRAL NONLINEARITY
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero-scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi-
tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above thelast code transition (111 . . . 110 to 111 . . . 111). The
error is expressed as a percentage of full scale.
POSITIVE FULL-SCALE ERROR
Positive full-scale error is the deviation of the last code transi-
tion (111 . . . 110 to 111 . . . 111) from the ideal input full-scale
voltage. For AIN1(+), the ideal full-scale input voltage is
(AIN1(–) + V
REF
/GAIN – 3/2 LSBs); for AIN2, the ideal full-
scale voltage is +4
×
V
REF
/GAIN – 3/2 LSBs. Positive full-scale
error applies to both unipolar and bipolar analog input ranges.
UNIPOLAR OFFSET ERROR
Unipolar offset error is the deviation of the first code transition
from the ideal voltage. For AIN1(+), the ideal input voltage is
(AIN1(–) + 0.5 LSB); for AIN2, the ideal input is 0.5 LSB
when operating in the unipolar mode.
BIPOLAR ZERO ERROR
This is the deviation of the midscale transition (0111 . . . 111
to 1000 . . . 000) from theideal input voltage. For AIN1(+), the
ideal input voltage is (AIN1(–) – 0.5 LSB); for AIN2, the ideal
input is –0.5 LSB when operating in the bipolar mode.
BIPOLAR NEGATIVE FULL-SCALE ERROR
This is the deviation of the first code transition from the ideal
input voltage. For AIN1(+), the ideal input voltage is (AIN1(–)
– V
REF
/GAIN + 0.5 LSB); for AIN2, the ideal input voltage is
(–4
V
REF
/GAIN + 0.5 LSB) when operating in the bipolar
mode.
POSITIVE FULL-SCALE OVERRANGE
Positive full-scale overrange is the amount of overhead available
to handle input voltages on AIN1(+) input greater than
(AIN1(–) + V
REF
/GAIN) or on the AIN2 of greater than +4
×
V
REF
/GAIN (for example, noise peaks or excess voltages due to
system gain errors in system calibration routines) without intro-
ducing errors due to overloading the analog modulator or to
overflowing the digital filter.
NEGATIVE FULL-SCALE OVERRANGE
This is the amount of overhead available to handle voltages on
AIN1(+) below (AIN1(–) – V
REF
/GAIN) or on AIN2 below
–4
×
V
REF
/GAIN without overloading the analog modulator or
overflowing the digital filter. Note that the analog input will
accept negative voltage peaks on AIN1(+) even in the unipolar
mode provided that AIN1(+) is greater than AIN1(–) and
greater than V
SS
– 30mV.
OFFSET CALIBRATION RANGE
In the system calibration modes, the AD7712 calibrates its offset
with respect to the analog input. The offset calibration range
specification defines the range of voltages that the AD7712 can
accept and still accurately calibrate offset.
FULL-SCALE CALIBRATION RANGE
This is the range of voltages that the AD7712 can accept in the
system calibration mode and still correctly calibrate full-scale.
INPUT SPAN
In system calibration schemes, two voltages applied in sequence
to the AD7712’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero to full-scale that the AD7712
can accept and still accurately calibrate gain.
相關(guān)PDF資料
PDF描述
AD7712 Signal Conditioning ADC(LC2MOS信號(hào)調(diào)節(jié)A/D轉(zhuǎn)換器)
AD7713* LC2MOS Loop-Powered Signal Conditioning ADC
AD7713AN LC2MOS Loop-Powered Signal Conditioning ADC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7712_04 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Signal Conditioning ADC
AD7712AN 功能描述:IC ADC SIGNAL COND LC2MOS 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
AD7712ANZ 功能描述:IC ADC SIGNAL COND LC2MOS 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
AD7712ANZ 制造商:Analog Devices 功能描述:IC ADC 24-BIT SIGMA DELTA
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