參數(shù)資料
型號： AD7711AAR
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： LC2MOS Signal Conditioning ADC with RTD Current Source
中文描述： 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封裝： SOIC-24
文件頁數(shù)： 2/27頁
文件大?。?/td> 222K
代理商： AD7711AAR
Parameter
STATIC PERFORMANCE
No Missing Codes
A, S Versions
1
Units
Conditions/Comments
24
22
18
15
12
See Tables I and II
±
0.0015
0.003
See Note 4
1
0.3
See Note 4
0.5
0.25
See Note 4
0.5
0.25
2
±
0.003
±
0.006
1
0.3
Bits min
Bits min
Bits min
Bits min
Bits min
Guaranteed by Design. For Filter Notches
≤
60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
Depends on Filter Cutoffs and Selected Gain
Filter Notches
≤
60 Hz
Typically
±
0.0003%
Excluding Reference
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
Output Noise
Integral Nonlinearity @ +25
°
C
T
to T
Positive Full Scale Error
2, 3
Full-Scale Drift
5
% FSR max
% FSR max
μ
V/
°
C typ
μ
V/
°
C typ
Unipolar Offset Error
2
Unipolar Offset Drift
5
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Bipolar Zero Error
2
Bipolar Zero Drift
5
μ
V/
°
C typ
μ
V/
°
C typ
ppm/
°
C typ
% FSR max
% FSR max
μ
V/
°
C typ
μ
V/
°
C typ
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Gain Drift
Bipolar Negative Full-Scale Error
2
@ +25
°
C
Excluding Reference
Typically
±
0.0006%
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
Bipolar Negative Full-Scale Drift
5
T
MIN
to T
MAX
ANALOG INPUTS/REFERENCE INPUTS
Common-Mode Rejection (CMR)
Common-Mode Voltage Range
Normal-Mode 50 Hz Rejection
7
Normal-Mode 60 Hz Rejection
7
Common-Mode 50 Hz Rejection
7
Common-Mode 60 Hz Rejection
7
DC Input Leakage Current
7
@ +25
°
C
T
MIN
to T
MAX
Sampling Capacitance
7
Analog Inputs
Input Voltage Range
9
100
V
SS
to AV
DD
100
100
150
150
10
1
20
dB min
V min to V max
dB min
dB min
dB min
dB min
pA max
nA max
pF max
At DC
For Filter Notches of 10, 25, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10, 30, 60 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10, 25, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 10, 30, 60 Hz,
±
0.02
×
f
NOTCH
For Normal Operation. Depends on Gain Selected
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
0 to +V
REF10
±
V
See Table III
nom
nom
Input Sampling Rate, f
S
Reference Inputs
REF IN(+) – REF IN(–) Voltage
11
+2.5 to +5
V min to V max
For Specified Performance. Part Functions with
Lower V
REF
Voltages
Input Sampling Rate, f
S
REFERENCE OUTPUT
Output Voltage
Initial Tolerance @ +25
°
C
Drift
Output Noise
Line Regulation (AV
DD
)
Load Regulation
External Current
NOTES
1
Temperature ranges are as follows: A Version, –40
°
C to +85
°
C; S Version, –55
°
C to +125
°
C.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I when using system calibration. These errors are 20
μ
V typical when using self-
calibration or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
This common-mode voltage range is allowed provided that the input voltage on AIN(+) and AIN(–) does not exceed AV
DD
+ 30 mV and V
SS
– 30 mV.
7
These numbers are guaranteed by design and/or characterization.
8
The analog inputs present a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum recommended source
resistance depends on the selected gain (see Tables IV and V).
9
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The absolute
voltage on the analog inputs should not go more positive than AV
DD
+ 30 mV or go more negative than V
SS
– 30 mV.
10
V
= REF IN(+) – REF IN(–).
11
The reference input voltage range may be restricted by the input voltage range requirement on the V
BIAS
input.
f
CLK IN
/256
2.5
±
1
20
30
1
1.5
1
V nom
% max
ppm/
°
C typ
μ
V typ
mV/V max
mV/mA max
mA max
pk-pk Noise 0.1 Hz to 10 Hz Bandwidth
Maximum Load Current 1 mA
AD7711A–SPECIFICATIONS
(AV
DD
= +5V
6
5%; DV
DD
= +5V
6
5%; V
SS
= 0 V or –5V
6
5%; REF IN(+) = +2.5V;
REFIN(–) = AGND; MCLK IN = 10MHz unless otherwise stated. All specifications T
MIN
to T
MAX
unless otherwise noted.)
–2–
REV. C
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