參數(shù)資料
型號: AD7711
廠商: Analog Devices, Inc.
英文描述: LC2MOS Signal Conditioning ADC with RTD Excitation Currents(RTD激勵電流LC2MOS信號調(diào)節(jié)A/D轉(zhuǎn)換器)
中文描述: LC2MOS信號調(diào)理模數(shù)轉(zhuǎn)換器(RTD的激勵電流LC2MOS信號調(diào)節(jié)的A / D轉(zhuǎn)換器與RTD激勵電流)
文件頁數(shù): 5/28頁
文件大小: 256K
代理商: AD7711
2
AD7711
–5–
REV. F
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
(A, S Versions)
Parameter
f
CLK IN4, 5
Units
Conditions/Comments
400
kHz min
Master Clock Frequency: Crystal Oscillator or Externally
Supplied for Specified Performance
10
0.4
×
t
CLK IN
0.4
×
t
CLK IN
50
50
1000
MHz max
ns min
ns min
ns max
ns max
ns min
t
CLK IN LO
t
CLK IN HI
t
r6
t
f6
t
1
Self-Clocking Mode
t
2
t
3
t
4
t
5
t
6
t
77
t
87
Master Clock Input Low Time; t
CLK IN
= 1/f
CLK IN
Master Clock Input High Time
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
SYNC
Pulsewidth
0
0
2
×
t
CLK IN
0
4
×
t
CLK IN
+ 20
4
×
t
CLK IN
+ 20
t
CLK IN
/2
t
CLK IN
/2
+ 30
t
CLK IN
/2
3
×
t
CLK IN
/2
50
0
4
×
t
CLK IN
+ 20
4
×
t
CLK IN
0
10
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns nom
ns nom
ns min
ns min
ns max
ns min
ns min
ns min
DRDY
to
RFS
Setup Time
DRDY
to
RFS
Hold Time
A0 to
RFS
Setup Time
A0 to
RFS
Hold Time
RFS
Low to SCLK Falling Edge
Data Access Time (
RFS
Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
t
9
t
10
t
14
t
15
t
16
t
17
t
18
t
19
SCLK High Pulsewidth
SCLK Low Pulsewidth
A0 to
TFS
Setup Time
A0 to
TFS
Hold Time
TFS
to SCLK Falling Edge Delay Time
TFS
to SCLK Falling Edge Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
(DV
DD
= +5V
6
5%; AV
DD
= +5V or +10 V
3
6
5%; V
SS
= 0 V or –5 V
6
10%; AGND = DGND =
0 V; f
CLK IN
= 10MHz; Input Logic 0 = 0 V, Logic 1 = DV
DD
, unless otherwise noted.)
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參數(shù)描述
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