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參數(shù)資料
| 型號： | AD7710ARZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT DIFF INP 24-SOIC |
| 標準包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1.03k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個差分，單極；2 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 778 (CN2011-ZH PDF) |
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REV. G
–26–
AD7710
Table VIII. 8XC51 Code for Writing to the AD7710
MOV SCON,#00000000B;
Configure 8051 for MODE 0
Operation and Enable Serial Reception
MOV IE,#10010000B;
Enable Transmit Interrupt
MOV IP,#00010000B;
Prioritize the Transmit Interrupt
SETB 91H;
Bring
TFS High
SETB 90H;
Bring
TFS High
MOV R1,#003H;
Sets Number of Bytes to Be Written
in a Write Operation
MOV R0,#030H;
Start Address in RAM for Bytes
MOV A,#00H;
Clear Accumulator
MOV SBUF,A;
Initialize the Serial Port
WAIT:
JMP WAIT;
Wait for Interrupt
INT ROUTINE:
NOP;
Interrupt Subroutine
MOV A,R1;
Load R1 to Accumulator
JZ FIN;
If Zero Jump to FIN
DEC R1;
Decrement R1 Byte Counter
MOV A,@R;
Move Byte into the Accumulator
INC R0;
Increment Address
RLC A;
Rearrange Data from LSB First
to MSB First
MOV B.0,C; RLC A; MOV B.1,C; RLC A;
MOV B.2,C; RLC A; MOV B.3,C; RLC A;
MOV B.4,C; RLC A; MOV B.5,C; RLC A;
MOV B.6,C; RLC A: MOV B.7,C; MOV A,B;
CLR 93H;
Bring A0 Low
CLR 91H;
Bring
TFS Low
MOV SBUF,A;
Write to Serial Port
RETI;
Return from Subroutine
FIN:
SETB 91H;
Set
TFS High
SETB 93H;
Set A0 High
RETI;
Return from Interrupt Subroutine
AD7710 to 68HC11 Interface
Figure 18 shows an interface between the AD7710 and the
68HC11 microcontroller. The AD7710 is configured for its
external clocking mode, while the SPI port is used on the 68HC11
in single-chip mode. The
DRDY line from the AD7710 is con-
nected to the Port PC2 input of the 68HC11, so the
DRDY line
is polled by the 68HC11. The
DRDY line can be connected to
the
IRQ input of the 68HC11 if an interrupt driven system is
preferred. The 68HC11 MOSI and MISO lines should be
configured for wire-OR operation. Depending on the interface
configuration, it may be necessary to provide bidirectional buff-
ers between the 68HC11 MOSI and MISO lines.
The 68HC11 is configured in master mode with its CPOL bit
set to a Logic 0 and its CPHA bit set to a logic 1. With a 10-MHz
master clock on the AD7710, the interface operates with all four
serial clock rates of the 68HC11.
AD7710
SDATA
SCLK
A0
RFS
TFS
PC0
MISO
SCK
PC1
PC2
MODE
PC3
DRDY
SYNC
68HC11
MOSI
SS
DVDD
Figure 18. AD7710 to 68HC11 Interface
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