參數(shù)資料
型號： AD7709BRUZ
廠商： Analog Devices Inc
文件頁數(shù)： 5/32頁
文件大?。?/td> 0K
描述： IC ADC 16BIT SIGMA-DELTA 24TSSOP
標準包裝： 62
位數(shù)： 16
采樣率（每秒）： 105
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 3.75mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應商設(shè)備封裝： 24-TSSOP
包裝： 管件
輸入數(shù)目和類型： 2 個差分，單極；2 個差分，雙極；4 個偽差分，單極；4 個偽差分，雙極
產(chǎn)品目錄頁面： 778 (CN2011-ZH PDF)
REV. A
AD7709
–13–
NOISE PERFORMANCE
Tables II and III show the output rms noise and output peak-to-
peak resolution in bits (rounded to the nearest 0.5 LSB) for a
selection of output update rates. The numbers are typical and
generated at a differential input voltage of 0 V. The output update
rate is selected via the SF7–SF0 bits in the Filter Register. It is
important to note that the peak-to-peak resolution figures
represent the resolution for which there will be no code flicker
within a six-sigma limit. The output noise comes from two sources.
The first is the electrical noise in the semiconductor devices
(device noise) used in the implementation of the modulator.
Second, when the analog input is converted into the digital
domain, quantization noise is added. The device noise is at a low
DIN
ADC STATUS REGISTER
(8 BITS)
CONFIGURATION REGISTER
(24 BITS)
FILTER REGISTER
(8 BITS)
ADC DATA REGISTER
(16 BITS)
REGISTER
SELECT
DECODER
DOUT
DIN
WEN R/W STBY OSCPD 0 0 A1 A0
Figure 9. On-Chip Registers
level and is independent of frequency. The quantization noise starts
at an even lower level but rises rapidly with increasing frequency
to become the dominant noise source. The numbers in the tables
are given for the bipolar input ranges. For the unipolar ranges,
the rms noise numbers will be the same as the bipolar range, but
the peak-to-peak resolution is now based on half the signal range,
which effectively means losing 1 bit of resolution.
ON-CHIP REGISTERS
The AD7709 is controlled and configured via a number of on-chip
registers, as shown in Figure 9 and described in more detail in the
following pages. In the following descriptions, set implies a Logic 1
state and cleared implies a Logic 0 state, unless otherwise stated.
Table II. Typical Output RMS Noise vs. Input Range and Update Rate for the AD7709 (Output RMS Noise in
V)
SF
Data Update
Input Range
Word
Rate (Hz)
20 mV
40 mV
80 mV
160 mV
320 mV
640 mV
1.28 V
2.56 V
13
105.3
1.50
1.60
1.75
3.50
4.50
6.70
11.75
69
19.79
0.60
0.65
0.95
1.40
2.30
255
5.35
0.35
0.37
0.51
0.82
1.25
Table III. Peak-to-Peak Resolution vs. Input Range and Update Rate for the AD7709 (Peak-to-Peak Resolution in Bits)
SF
Data Update
Input Range
Word
Rate (Hz)
20 mV
40 mV
80 mV
160 mV
320 mV
640 mV
1.28 V
2.56 V
13
105.3
12
13
14
15
15.5
16
69
19.79
13
14
15
16
255
5.35
14
15
16
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