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參數(shù)資料
| 型號： | AD7707BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V/5 V, +-10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC |
| 中文描述： | 3-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 4/40頁 |
| 文件大?。?/td> | 316K |
| 代理商： | AD7707BR |
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REV. A
–4–
AD7707–SPECIFICATIONS
Parameter
B Version
1
Units
Conditions/Comments
POWER REQUIREMENTS (Continued)
DV
DD
Current
17
Digital I/Ps = 0V or DV
DD
. External MCLK IN
Typically 0.06mA. DV
DD
= 3V. f
CLK
IN
= 1MHz
Typically 0.13 mA. DV
DD
= 5V. f
CLK
IN
= 1MHz
Typically 0.15mA. DV
DD
= 3V. f
CLK
IN
= 2.4576MHz
Typically 0.3mA. DV
DD
= 5V. f
CLK
IN
= 2.4576MHz
0.080
0.15
0.18
0.35
See Note 20
mA max
mA max
mA max
mA max
dB typ
Power Supply Rejection
19
Normal Mode Power Dissipation
17
AV
DD
= DV
DD
= +3 V. Digital I/Ps = 0 V or DV
DD
.
External MCLK IN Excluding Dissipation in the AIN3
Attenuator
Typically 0.84 mW. BUF = 0. f
CLK
IN
= 1MHz, All Gains.
Typically 1.53 mW. BUF = 1. f
CLK
IN
= 1MHz, All Gains.
Typically 1.11 mW. BUF = 0. f
CLK
IN
= 2.4576 MHz,
Gain = 1 to 4.
Typically 1.9 mW. BUF = 1. f
CLK
IN
= 2.4576 MHz,
Gain = 1 to 4.
AV
DD
= DV
DD
= +5 V. Digital I/Ps = 0V or DV
DD
.
External MCLKIN
Typically 1.75 mW. BUF = 0. f
CLK
IN
= 1MHz, All Gains.
Typically 2.9 mW. BUF = 1. f
CLK
IN
= 1MHz, All Gains.
Typically 2.6 mW. BUF = 0. f
CLK
IN
= 2.4576 MHz.
Typically 3.75 mW. BUF = 1. f
IN
= 2.4576 MHz.
External MCLK IN = 0 V or DV
DD
. Typically 9
μ
A.
AV
DD
= +5 V
External MCLK IN = 0 V or DV
DD
. Typically 4
μ
A.
AV
DD
= +3 V
1.05
2.04
1.35
mW max
mW max
mW max
2.34
mW max
Normal Mode Power Dissipation
17
2.1
3.75
3.1
4.75
18
mW max
mW max
mW max
mW max
μ
A max
Standby (Power-Down) Current
18
8
μ
A max
NOTES
Temperature range as follows: B Version, –40
°
C to +85
°
C.
2
These numbers are established from characterization or design at initial product release.
3
A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I and III for the low level input channels AIN1
and AIN2. This applies after calibration at the temperature of interest.
4
Recalibration at any temperature will remove these drift errors.
5
Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.
6
Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.
7
Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and full-scale error–bipolar zero error for
bipolar ranges.
8
Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.
9
Error is removed following a system calibration.
10
This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than AV
+ 30 mV or go more negative
than AGND – 100mV. Parts are functional with voltages down to AGND – 200 mV, but with increased leakage at high temperature.
11
The analog input voltage range on AIN(+) is given here with respect to the voltage on LCOM on the low level input channels (AIN1 and AIN2) and is given with
respect to the HCOM input on the high level input channel AIN3. The absolute voltage on the low level analog inputs should not go more positive than AV
+
100mV, or go more negative than GND– 100mV for specified performance. Input voltages of AGND – 200 mV can be accommodated, but with increased leakage
at high temperature.
12
V
= REF IN(+) – REF IN(–).
13
These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
14
Sample tested at +25
°
C to ensure compliance.
15
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will
output all 0s.
16
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30mV or go more negative than AGND –
30mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
17
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
DD
current and power dissipation will vary depending on
the crystal or resonator type (see Clocking and Oscillator Circuit section).
18
If the external master clock continues to run in standby mode, the standby current increases to 150
μ
A typical at 5 V and 75
μ
A at 3 V. When using a crystal or
ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation
depends on the crystal or resonator type (see Standby Mode section).
19
Measured at dc and applies in the selected passband. PSRR at 50Hz will exceed 120dB with filter notches of 25 Hz or 50Hz. PSRR at 60Hz will exceed 120dB
with filter notches of 20 Hz or 60Hz.
20
PSRR depends on both gain and AV
DD
.
Low Level Input Channels, AIN1 and AIN2
High Level Input Channel, AIN3
Gain
AV
DD
= 3 V
AV
DD
= 5 V
1
86
90
2
78
78
4
85
84
8–128
93
91
Gain
AV
DD
= 3 V
AV
DD
= 5 V
1
68
72
2
60
60
4
67
66
8–128
75
73
Specifications subject to change without notice.
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