參數(shù)資料
型號： AD7706EB
廠商： Analog Devices, Inc.
英文描述： High Performance Switched Capacitor Universal Filter; Package: PDIP; No of Pins: 14; Temperature Range: 0°C to +70°C
中文描述： 3伏/ 5伏1毫瓦2-/3-Channel 16位Σ-Δ模數(shù)轉換器（264.12十一）
文件頁數(shù)： 20/32頁
文件大小： 264K
代理商： AD7706EB
AD7705/AD7706
–20–
REV. A
range and the top of its input range) has to take into account the
limitation on the positive full-scale voltage. The amount of
offset which can be accommodated depends on whether the
unipolar or bipolar mode is being used. Once again, the offset
has to take into account the limitation on the positive full-scale
voltage. In unipolar mode, there is considerable flexibility in
handling negative (with respect to AIN(–) on the AD7705 and
with respect to COMMON on the AD7706) offsets. In both
unipolar and bipolar modes, the range of positive offsets that
can be handled by the part depends on the selected span. There-
fore, in determining the limits for system zero-scale and full-
scale calibrations, the user has to ensure that the offset range
plus the span range does exceed 1.05
×
V
REF
/GAIN. This is best
illustrated by looking at a few examples.
If the part is used in unipolar mode with a required span of
0.8
×
V
REF
/GAIN, the offset range the system calibration can
handle is from –1.05
×
V
REF
/GAIN to +0.25
×
V
REF
/GAIN. If
the part is used in unipolar mode with a required span of V
REF
/
GAIN, the offset range the system calibration can handle is
from –1.05
×
V
REF
/GAIN to +0.05
×
V
REF
/GAIN. Similarly, if
the part is used in unipolar mode and required to remove an
offset of 0.2
×
V
REF
/GAIN, the span range the system calibration
can handle is 0.85
×
V
REF
/GAIN.
AD7705/AD7706
INPUT RANGE
(0.8
3
V
REF
/GAIN TO
2.1
3
V
REF
/GAIN)
UPPER LIMIT ON
AD7705 INPUT VOLTAGE
NOMINAL ZERO
SCALE POINT
OFFSET CALIBRATIONS MOVE
INPUT RANGE UP OR DOWN
LOWER LIMIT ON
AD7705/AD7706 INPUT VOLTAGE
–1.05
3
V
REF
/GAIN
–0V DIFFERENTIAL
GAIN CALIBRATIONS EXPAND
OR CONTRACT THE
AD7705/AD7706 INPUT RANGE
1.05
3
V
REF
/GAIN
Figure 13. Span and Offset Limits
If the part is used in bipolar mode with a required span of
±
0.4
×
V
REF
/GAIN, the offset range the system calibration can
handle is from –0.65
×
V
REF
/GAIN to +0.65
×
V
REF
/GAIN.
If the part is used in bipolar mode with a required span of
±
V
REF
/GAIN, then the offset range which the system calibration
can handle is from –0.05
×
V
REF
/GAIN to +0.05
×
V
REF
/GAIN.
Similarly, if the part is used in bipolar mode and required to
remove an offset of
±
0.2
×
V
REF
/GAIN, the span range the sys-
tem calibration can handle is
±
0.85
×
V
REF
/GAIN.
Power-Up and Calibration
On power-up, the AD7705/AD7706 performs an internal reset
that sets the contents of the internal registers to a known state.
There are default values loaded to all registers after power-on or
reset. The default values contain nominal calibration coefficients
for the calibration registers. However, to ensure correct calibra-
tion for the device, a calibration routine should be performed
after power-up.
The power dissipation and temperature drift of the AD7705/
AD7706 are low and no warm-up time is required before the
initial calibration is performed. However, if an external refer-
ence is being used, this reference must have stabilized before
calibration is initiated. Similarly, if the clock source for the part
is generated from a crystal or resonator across the MCLK pins,
the start-up time for the oscillator circuit should elapse before a
calibration is initiated on the part (see below).
MCLK IN
MCLK OUT
CRYSTAL OR
CERAMIC
RESONATOR
C1
C2
AD7705/AD7706
Figure 14. Crystal/Resonator Connection for the
AD7705/AD7706
USING THE AD7705/AD7706
Clocking and Oscillator Circuit
The AD7705/AD7706 requires a master clock input, which
may be an external CMOS compatible clock signal applied to
the MCLKIN pin with the MCLKOUT pin left unconnected.
Alternatively, a crystal or ceramic resonator of the correct fre-
quency can be connected between MCLKIN and MCLKOUT
as shown in figure 6, in which case the clock circuit will function
as an oscillator, providing the clock source for the part. The
input sampling frequency, the modulator sampling frequency,
the –3dB frequency, output update rate and calibration time
are all directly related to the master clock frequency, f
CLKIN
.
Reducing the master clock frequency by a factor of 2 will halve
the above frequencies and update rate and double the calibra-
tion time. The current drawn from the V
DD
power supply is also
related to f
CLKIN
. Reducing f
CLKIN
by a factor of 2 will halve the
digital part of the total V
DD
current but will not affect the cur-
rent drawn by the analog circuitry.
Using the part with a crystal or ceramic resonator between the
MCLK IN and MCLK OUT pins generally causes more cur-
rent to be drawn from V
DD
than when the part is clocked from
a driven clock signal at the MCLK IN pin. This is because the
on-chip oscillator circuit is active in the case of the crystal or
ceramic resonator. Therefore, the lowest possible current on
the AD7705/AD7706 is achieved with an externally applied
clock at the MCLK IN pin with MCLK OUT unconnected,
unloaded and disabled.
The amount of additional current taken by the oscillator de-
pends on a number of factors—first, the larger the value of
capacitor (C1 and C2) placed on the MCLKIN and MCLKOUT
pins, the larger the current consumption on the AD7705/
AD7706. Care should be taken not to exceed the capacitor
values recommended by the crystal and ceramic resonator
manufacturers to avoid consuming unnecessary current. Typical
values for C1 and C2 are recommended by crystal or ceramic
resonator manufacturers, these are in the range of 30pF to
50pF and if the capacitor values on MCLK IN and MCLK
OUT are kept in this range they will not result in any excessive
current. Another factor that influences the current is the effec-
tive series resistance (ESR) of the crystal that appears between
the MCLK IN and MCLK OUT pins of the AD7705/AD7706.
As a general rule, the lower the ESR value the lower the current
taken by the oscillator circuit.
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